Homework Assignment #2

EE 477 Fall 2008 Professors Parker and Zadeh

Due 9/22/08 in class or via the assignment function on DEN at 11:59 PM

1. (15%) Design a level-sensitive latch at the transistor level that can be set and reset. The latch should be set asynchronously, and should be reset when the clock is high. Set means the output of the latch is high, and reset means the output of the latch is low. Asynchronously means there is no load or clock signal required to set the latch. The latch has two inputs plus the feedback path. You should be able to multiplex between both inputs and the feedback. Show the transistor circuit diagram. Use NOR and INVERT gates for the 3-input mux at the input to the latch. The latch should load when clock is low.

2. (10%) For your latch in Problem 1, you had to design a multiplexer to select between one of two inputs or the latch output using only NOR complementary CMOS gates. Does your design use more transistors than a mux built with transmission gates?

3. (20%) Draw a transistor (circuit) level diagram for a compound gate that implements the following Boolean function OUT =/[(C+D+E)(F+GH)]. / means "NOT". Label the sources and drains of all the transistors.

4. (10%) Sketch the side view (slice down into the silicon) of a stacked contact that connects metal2 to metal5 using colored pens or pencils.

5. (10%) Sketch the steps in the photolithographic process necessary to create and pattern the polysilicon.

6. (5%) Why do we tie the N-Well to Vdd?

7. (15%) In the attached figure, show the cross-section down into the silicon along the vertical black line.

8. (5%) Where are bipolar parasitic transistors formed?

9. (10 %) Why do we have minimum sizes of metal used for interconnections? What problem are we avoiding?