Homework Assignment #1
EE 477 Fall 2008 Professors Parker and Zadeh
Hardcopies due in the course boxes on the first floor of EEB 9/15/2008 5 PM
Ecopies due 11:59 PM 9/15/08 using the "Assignment" Function on DEN
To ensure academic integrity, please use a cover page on your homework hard copies that does not contain any work.
1. (5%) Give the Boolean expression for a single bit full adder carry_out with inputs Ci-1, Ai and Bi and output Ci.
2. (10%) Show an implementation of the full adder carry_out at the gate level using complementary NAND, NOR and INV gates. You may not use XOR or XNOR gates.
3. (15%) Show an implementation of the full adder carry_out from Problem 2 at the circuit (transistor) level ( for an example of complementary CMOS NAND gates and inverter, See Fig. 1)
4. (10%) Show a compound gate implementation of the full adder carry_out at the circuit (transistor) level, similar to the compound gate shown in Fig. 2. You may need an additional inverter at the output to get a positive carry_out, instead of carry_out bar.
5. (10%) Show a stick diagram of a 5-input NAND gate, labeling the layers or using colors for the different layers as shown in lecture.
6. (20%) . Use the same style of design as problem 3 (See Fig. 1 - use only NAND, NOR, INVERT gates) to build a transistor-level circuit that implements a Boolean function that has a high output only if any 3,4 or 5 of 5 inputs A, B, C, D and E are high, as long as the input F is low, or has a high output only if A, B, C and D are high, regardless of the values of E and F. The output is low otherwise.
Note: You can assume the complements of the inputs also to be inputs to the circuit. You can use gates with any number of inputs.
7. (20%) Again refer to the style of compound gate circuit used in lecture (See Fig. 2 for an example).
a) Redesign your circuit from Problem 6 at the transistor level using a compound gate. You might have to invert the output with an inverter. Show the compound gate transistor diagram. Compare the number of transistors to the original design in Problem 6.
b) Now redesign your circuit from Problem 6 at the transistor level using only NAND gates and inverters. Again compare the transistor count. Show your work. You can use gates with any number of inputs.
8. (20%) Show a logic design at the gate level of a 4-input mux. Use only NAND and NOR gates and inverters.