EE477 - f07 lab3

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3

Module Design, Cadence and SPICE

Due December 11 12, 2007, 12:00 Midnight

updated to extend due date and correct list to turn in

This lab addresses the design of a special-purpose circuit. The basic building block in the circuit is a very simplified digital neuron, along with a D flip flop. You will build a small network with this neuron and the D flip flop as basic building blocks.

The digital neuron

There are four data inputs to the neuron, A, B, C, and D, an inhibitory input I (asserted low), load, reset, and a clock. You can assume /clock is an input too but you need to generate other inverted inputs. The neuron contains a flip flop, and the output of the flip-flop represents the output of the neuron. The neuron "fires" when 3 of the 4 data inputs are high, as long as I is held high, and after the positive edge of the clock, the output of the flip-flop goes from low to high. After the next rising clock, the flip-flop output falls. The neuron cannot "fire" two clock cycles in a row. Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance. The I input is not an external input and you can use it for any purpose you would like. A block diagram of the neuron is shown below.

The Neural Network

For the project, you are to assemble a "neural net" using 4 of these neurons, and 2 D flip flops acting as "relay" neurons. The D flip flops (relay neurons) load new inputs every cycle.The network detects edges moving from the top to the bottom of the network, from R₁to R₁₂. The edges detected are dark (0) followed by light (1). The edges move 4 spaces every clock cycle. So on clock cycle 1, if R₁ input is a 1, on clock cycle 2, R₅ will be a 1. Only one light bar 2 bits wide (dark to light to dark transition) will be in the "field of view" at a time.

You can use any combination of multiple clocks you wish, but only clock and /clock are clock inputs to the circuit and you will have to design circuits to generate the other clocks. /load is not an input to the circuit. You need to generate it if you need it. You can assume reset is asserted low if you like.

You should use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells or the transistor sizes unless the rise/fall times do not meet the requirements of lab 1. However, you can modify the layout in minor ways if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Make sure your ohmic contacts meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course they should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts.

You can use metal layers 1, 2 and 3 for the neuron. You can use metal layers 1-5 for the entire neural network.

The diagram below shows how the neurons are to be connected.

The Laboratory Goal

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.

The Laboratory Steps

1. Design your circuit and create a Cadence circuit (schematic) diagram and a Cadence layout using the cells you have already designed. You cannot design new cells for Lab 3. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram for your neuron. Use LVS to verify your layout prior to SPICE simulation. Important note: Any pins in your layout labeled the same should be physically connected.

2. Simulate your schematic and layout with SPICE to ensure that your design works correctly The inputs to your project circuit should be named clock, load, R₁, R₂, R₃, R₄, R₅, R₆,R₇, R₈, R₉, R₁₀,R₁₁, R₁₂, and reset. The output should be named LtoRedge. It is important you follow this naming convention so we can verify that your circuit works.

Use the following sequence of inputs (See timing diagram below for exact details):

a) Reset all flip flops (even though reset is shown asserted high you could assert it low) using whatever clock settings you need. This will vary depending on how you implemented reset.

b) Unassert Reset and then set load , R₁, and R₂ to 1. Set load high and keep it high. All other R inputs should be 0. Clock the circuit. Then set R₅ and R₆ high, and all other R inputs low. Clock the circuit again. Then set R₉, and R₁₀ to high and all other Rinputs low and clock again. Your output LtoRedge should be high after the third upward transition of the clock.

c) Now lower all R inputs except raise R₁₁ and R₁₂ . Then raise clock. Then lower all R inputs except raise R₉ and R₁₀. Clock again twice. Now your output should continue low after three positive clock edges.

d) Now hold your load input low. Return to the input sequence in part a. After three clock cycles, the output should remain low.

e) Now hold R₁, and R₂high for two clock cycles, and show the output of neuron 1 (N1) to verify that it does not fire twice in a row. This case is not shown in the timing diagram.

3. Simulate your circuit with SPICE. The delay you should measure with SPICE is the clock cycle. The faster your clock cycle, the faster your circuit will function.

4. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design.

5. Upload your report to the assignments function of Blackboard, incliding your layout and simulation files as a TAR file as in lab 2 so that we can test (simulate) your circuit to be sure it performs as specified Be sure to include your SPICE input files for the project.

Testing Strategy

Here is a testing strategy that might be useful to you: Build the majority gate schematic in Cadence and test it using SPICE. Add the flip flop and any logic needed to keep the flip flop from firing two clock cycles in a row. Test the entire "neuron." Now create your neural network schematic in Cadence and test it. Use the same incremental strategy to perform your layout and to test your layout.

Timing Diagram

Lab Report Contents:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number.
A description of the neuron and network you built, including a transistor-level or gate-level circuit diagram printed from Cadence.
The neuron and neural network layout screen capture.
A description of the simulation experiments you ran with SPICE
SPICE input netlist and simulation files generated by Cadence
SPICE outputs for the neural network schematic and layout as shown in MWAVES images.

Items 1-4 and 6 should all be in a single report. Tar this report along with the files specified in item 5, and upload to the assignments page of the blackboard.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.