EE477 - f07 lab2

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2

Latch/FF Design, Layout and SPICE Simulations

Due November 21, 2007 11:59 AM

V_dd = 2.5 v.

A note about well and substrate contacts: Make sure your ohmic contacts meet the following requirement: Every cell should have a well and substrate contact. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts.

Part 1: Cell Layout SPICE Simulations

Simulate the cell layouts you designed in Lab 1 using SPICE, attaching the inverter cell layout as a "load" to the output of each cell. To do this, create a new cell that contais the cell you are testing and also the load (inverter) cell. For the simulation use the same inputs in the same order as you did for the schematic simulations, including your worse-case simulations. Your device sizes should give the same rise and fall times you were instructed to attain in Lab 1. You can use these values for transistor betas: βn (beta)= 109.7 W/L μ A(microamps)/V² and βp (beta)= 25.5 W/L μ A/V² . Note the rise and fall times at the outputs of each cell. Use a rise and fall time for the inputs signals of .1 ns. You will need to insure when you extract the SPICE file from the layout that you include all parasitic capacitances.

The report on this part of your lab should contain a title page, a list of all the cells you simulated, layout images, and the SPICE simulation outputs in the form of MWAVE images. Also include a discussion of cell rise and fall times and a comparison to the simulation results you got for Lab 1. All these parts should be in a single lab report file in a standard format like .doc, .pdf, or .ppt. Tar this lab report with the SPICE netlist and stimulus files generated by Cadence, and the lab report and files from Part 2, described below. The report should be typed, not handwritten.

Part 2: LATCH and FLIP-FLOP DESIGN

1. Use the cells you have already constructed to design a latch, and use two latches to build a CMOS D flip-flop schematic in Cadence. Assume the flip-flop is clocked, and that clock, /clock, synchronous load and synchronous /load are inputs to your design. You must include asynchronous reset signals in your circuit. Load is active high. The flip-flop should be positive edge triggered. The clock signal should not be gated (in other words, the clock signal should not pass through any logic gates before arriving at the flip-flop). Optional: You can construct a transmission gate multiplexer instead of using the gates you already designed. There is no guarantee that your circuit will be smaller or faster if you do, but the odds are that it will be.

The transistors in the gates used in the flip-flop should be sized as they were to be sized for Lab 1. Do not use ratioed (pseudoNMOS) logic. Do not use dynamic logic or dynamic storage (not covered yet).

2. Simulate the flip-flop schematic you built in Cadence using SPICE again assuming the data D, clock, /clock, reset, load and /load signals are inputs to your design. Be sure to try all possible combinations of data inputs versus present state of the flip flop, using the waveforms shown below. Start with clock low, D low and load high. Be sure test reset as well. For the simulations, attach your inverter schematic as a "load" to the flip-flop output. Adjust the timing of your clock to be as fast as possible and still have the circuit work properly. The waveforms shown below show the order of changes of inputs you are to use for the simulations. Reset is not shown and should be simulated with clock and load low.

3. Use the same layout methodology you used in Lab #1 to layout the flip flop, using only the bottom two layers of metal, metal 1 and metal 2.

Extract SPICE (netlist) files for the flip-flop layout from Cadence and simulate with V_in (Data) changing from 0 v. to Vdd (2.5 v.) and then Vdd to 0 v. For the simulations, attach your inverter cell layout as a "load" to the flip-flop output. Again assume the clock and load signals are inputs to your circuit. Proper functioning includes having the low output be less than .1 V_dd and the high output being greater than .9 V_dd.The clock and all input signals should have a rise and fall time of .1 ns. Plot V_in and V_out versus time using MWAVES. Note the delay between V_in changing and V_out changing. Use the definitions of delay given in the text as the time between the input achieving 50% of its final value and the output achieving 50% of its final value. The clock should have a 50% duty cycle. Make the clock as fast as you can and still get correct results.

What to turn in for Part 2: Your lab 2 part 2 should contain the following items:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number.
A description of the flip-flop you built, including a transistor-level or gate-level circuit diagram printed from Cadence.
The flip-flop layout screen capture
A description of the simulation experiments you ran with SPICE
SPICE input netlist and simulation files generated by Cadence
SPICE outputs for the flip-flop schematic and layout as shown in MWAVES images.

Items 1-4 and 6 should all be in a single report. Tar this report along with the files specified in item 5 and the items from part 1 of this lab, and upload to the assignments page of the blackboard.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.