Homework Assignment #5

Prof. Parker Due November 9, 2007 at 4:30 PM in EEB 106. Electronic submissions due at 11:59 PM EE 477 Fall 2007

Edited Nov. 5 to clarify problem 1. Changes in Green italics.

Assume V_dd = 2.5 v. for these problems. Assume V_tp is -.7 V. Assume V_tn is .7 V. Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. ε0 (epsilon) = 8.85 X 10 -14 F/cm and εoxide(epsilon) = 3.9 lambda = .25 microns. Cjbsn = 17.27 x 10-4 pF/ μm2 and Cjbswn = 4.17 x 10-4 pF/ μm (micrometer). Cjbsp = 18.8 x 10-4 pF/ μm2and Cjbswp = 3.17 x 10-4 pF/ μm (micrometer). x_j (diffusion depth) = 0.1 microns.

1. a) (10%) Size the transistors in a 6-input NOR gate so that the worst-case rise and fall times are equal, assuming the smallest transistors are unit size.

b) (5%) Show an equivalent circuit of the NOR gate, with all capacitances shown. For the equivalent circuit, you can assume worst case rise or fall time.

2. (10%) Size the transistors in a 4-input NAND gate so that the rise and fall times are equal, assuming the smallest transistors are unit size. Label the inputs W, X, Y and Z, and explain the combination of input changes that gives worst case rise and fall times.

3. (10%) An off-chip inverter using a special kind of CMOS circuit outputs a "high" signal when the inverter output>=2 .4 v, and a "low" when the inverter output <= .4 v. The on-chip inverter receiving the signal sees a high at a minimum of 1.3 v, and a low at a maximum of .7 v. If the noise signal has an amplitude swing of plus or minus .4 v., are the noise margins adequate?

4 a) (10%) For the circuit shown in the spring 2007 homework 2 solution to problem 2a, identify a critical path on the PMOS side and the NMOS side, ignoring the output inverter.

b) (10%) Size the transistors on the critical path so that rise and fall times = rise and fall times of an inverter with unit size NMOS transistor and PMOS transistor 4 X width of NMOS transistor.

c) (10%) For the leftmost PMOS pathway, CAD, size those transistors so the delays equal the delays in the PMOS critical path.

5. (15%) Compute the gate capacitance of an NMOS transistor that has width dimensions 5.5 times minimum size, and minimum length.

6. (20%) Compute the diffusion capacitance of the drain of an NMOS transistor that has dimensions 8 lambda wide by 4 lambda long. Use the method described in the lecture and the text. Note that this method might differ from past homework solutions.