A. Parker

EE 477L Fall 2007

Homework Assignment #4

Due 4:30 PM 10/5/07

Assume for the problems below that Vdd = 2.5 v, V_tp0 is -.6 v. and V_tn0 is .6 V. V_tpbodyeffect is -.8 v. and V_tnbodyeffect is .8 V.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

1. a) (5 %) Identify the sources and drains in a transmission gate at t=0+ when V_in = 1.5 v. and V_out = 0.5 v. V_gn = 2.5v, and V_gp = 0v.

b) (10 %) What regions are the two transistors in when t approaches infinity? Be sure to justify your answers.

2. (10 %) An NMOS transistor has V_DS = 1.4 V. V_S = 1.1 V. Is the transistor is in the linear region of operation when V_GS = 1.7 V.?

3. (10 %) A PMOS transistor has V_GS = -1.0 V , V_DS = -0.9 V. V_S = 1.0 v. What region of operation is it in? Now assume V_GS = -1.2 V and V_DS = -.2 V. What region of operation is the transistor in?

4.(5 %) A PMOS transistor passes a weak 0. Does body effect make the 0 stronger or weaker?

5. a) (10 %) Use the left edge algorithm to connect the common inputs that are in the following order from left to right (beginning and ending points for each line are shown in parenthesis:

A(0,7), B(0,9), C(1,8), D(8,12), E(10,13), F(4,7)

Edited to add the following comment: Note that when a wire ends at a point a new wire must start to the right of that point if it is in the same track. A wire that ends at point 8, for example, can only share the track with wires that start at points 9 or further to the right. Wires that start and end at the same point are connected.

For drawing ease, assume all metal 2 connections come from the top, and make all metal 1 connections left to right.

b) (5%) Show the stick diagram for the connections, assuming horizontal connections (connections running along the channel) are in metal 1, and vertical ones are in metal2.

6. (5%) What is the advantage of using a gate insulating material that is thicker than normal?

7. (10%) Compute the drain current flow I_DSin a PMOS transistor when V_DS = -2.2 v, and V_GS = -1.7 V. Assume the transistor width is 24 lambda and the length is 3 lambda.

8. (10%) Compute the channel resistance of an NMOS transistor when V_gs = 1.7 v and V_ds = .9 v. V_s=0.0 V.

The last two questions should be answered after the Tues/Wed lecture:

9. (10 %) An inverter has the transistors sized so that the beta of the PMOS transistor is 4 times the beta of the NMOS transistor. As the input rises from 0.0 v towards Vdd, would the output fall faster or slower than if the betas were equal?

10. (10%) An inverter has the transistors sized to have equal betas (k's). What regions of operation are the transistors in when Vin = 1.35 V?