A. Parker

EE 477L Fall 2007

Homework Assignment #3Due by 5:00 PM 9/28/07 *

1. (25 %) Use the compound gate from Assignment #1 Problem 7a. Label the sources and drains of all transistors. Show an identical Euler path for both NMOS and PMOS transistors by listing transistor inputs on both paths. You can rearrange the transistors if you need to to get identical Euler paths. If you optimized the Boolean equation for Assignment 1 the way the solution did, and you have trouble finding an Euler path, try an unoptimized compound gate to find an Euler path.

2. (30%) Give a stick diagram for the compound gate in Problem 1 above, using the Euler paths you found.

3. (20 %) Connect the common inputs in the stick diagram using the left edge algorithm, using metal 1.

4. (10 %) Why do we have a gate extension with polysilicon?

5. (5 %) Design rules governing the sizes of features help us avoid major failure. Are we interested in the maximum sizes or minimum sizes to avoid failure?

6. (10 %) What is a unit-size transistor?

* We will work on a homework submission plan for this and future assignments. Late homework can be submitted under my door.