Homework Assignment #2

EE 477 Fall 2007 Professor Parker and Mr. Zadeh

Due 9/21/07 5 PM in the box in EEB 106 or in the digital drop box by 11:59 PM

1. (15%) Design a level-sensitive latch at the transistor level that contains an inverter in the forward path and a NOR gate in the feedback path where an inverter is shown in the lecture notes. Can your latch be set or reset asynchronously? Set means the output of the latch is high, and reset means the output of the latch is low. Asynchronously means there is no load or clock signal required to set or reset the latch. Show the transistor circuit diagram. Use NOR and INVERT gates for the mux at the input to the latch. The latch should load when clock is low.

2. (10%) For your latch in Problem 1, you had to design a multiplexer to select between one of two inputs using only NOR and INVERT complementary CMOS gates. Does your design use more transistors than a mux built with transmission gates?

3. (20%) Draw a transistor (circuit) level diagram for a compound gate that implements the following Boolean function OUT = /[(AB + DEF + HJ)*(CG+MN)]. Label the sources and drains of all the transistors.

4. (20%) Use Cadence schematic capture to draw a schematic of your design from Problem 6 of Homework 1. You can use default-size transistors. Capture your schematic. If you want the black background you can use a "print screen" (PC) or "Grab" (MAC) command. If you want black circuit on white background (better for printed schematics) use the following procedure: Open your schematic. Pull down the design menu and click on plot, then on submit. A submit plot window will open up. Click on plot options in the lower right corner and select send plot only to file and give a file name. The filename should be of the form myfilename.ps. Then type distill myfilename.ps to get a pdf file.

5. (10%) Describe the steps in the photolithographic process necessary to create and pattern the poly layer.

6. (5%) What is the role of ohmic contacts?

7. (15%) In the attached figure, show the cross-section down into the silicon along the vertical black line.

8. (5%) MOS parasitic transistors usually have what material in their "gates"?