Homework Assignment #1

EE 477 Fall 2007 Professor Parker/Mr. Zadeh

Due 4:30 PM 9/13/07


Please use the digital drop box on the den website for the first 5 problems of this assignment. That way we can make sure all of you know how to use that facility.

The following 5 problems are worth 5 points each. There are no wrong answers for these problems.


1. Please give your name exactly as USC has you listed.

2. Please give any nicknames you might use.

3. Please tell me your degree program (e.g., MSEE, PHD Material Science). It is especially important that we know whether you are a BS, MS or PhD student.

4. Please tell me the CAD tools you have used in the past.

5. Please tell me what % of this class probably duplicates your previous coursework, and list the topics you think are duplicated.


Turn in the remainder of the problems to the box outside Professor Parker's office.


6. (20%) The computation shown in the attached figure is performed using complementary NAND/NOR/INVERT circuitry (See Fig. 1). Use the same style of design (use only NAND, NOR, INVERT gates) to build a transistor-level circuit that implements a Boolean function that has a high output if any 3 or 4 of 4 inputs A, B, C, and D are high, as long as the input E is low. If E is high, the output is always low regardless of the values of A, B, C or D.

You can assume the complements of the inputs also to be inputs to the circuit. You can use gates with any number of inputs.

7. (20%) The decrement computation shown in the attached figure is a compound gate (See Fig. 2).

a) Redesign your circuit from Problem 6 at the transistor level using a compound gate. You might have to invert the output with an inverter. Show the compound gate transistor diagram. Compare the number of transistors to the original design in Problem 6.

b) Now redesign your circuit from Problem 6 at the transistor level using only NAND gates. Again compare the transistor count. Show your work. You can use gates with any number of inputs.

8. (20%) Sketch a stick diagram of a transmission gate 2-input mux. You do not need to use the cell design method shown in class for this exercise. The text (and the Internet) might have some example stick diagrams for you to follow.