University of Southern California

Department of Electrical Engineering - Systems

EE 477L Design Project

Dr. Parker

Module Design using Magic, IRSIM and SPICE

This Project addresses the design of a special-purpose circuit. The circuit you are to design performs the following function: It reads in a 1-bit value from a single-bit data line for every clock cycle, for 8 cycles. It sends the data part way across the chip, 4 mm in distance, to a receiver. The data can be sent in any way you like, and as many bits at a time as you like. The receiver outputs the 8-bit word. The 8-bit word remains at the outputs of the receiver until the next 8-bit word is ready to be output The circuit never halts. You have as input to the circuit a clock, and /clock, along with a single data input. You may also use as input a reset signal if you need it.

For this project, you can use any layout strategy you choose, but once you pick a layout strategy for your cells, you should continue that strategy through the project. The goal is to minimize the area·delay (the product of area and delay). The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com.

The project is divided into three lab assignments. In Laboratory Assignment #1, you designed the NAND, NOR and INVERT cells that you will need for the project and performed IRSIM and SPICE simulations of the cells. In Laboratory Assignment #2 you will design the flip-flop cell, and perform simulations of your cell. In Laboratory Assignment #3 you will use the cells you designed in Labs 1 and 2 to build the special-purpose circuit. You will be allowed in Lab 3 to modify your inverter's transistor sizes as desired.

Area will be measured by the rectangular bounding boxes that surround your circuit. You can use multiple boxes, one for the sender, one for each interconnection segment between sender and receiver (there will be multiple segments if you insert buffers), one for each buffer on the interconnection (if you use buffers), and one for the receiver. Delay will be measured by the delay from the falling edge of the clock that causes the first bit to be input into the sender until the falling edge of the clock that outputs the 8-bit word from the receiver.

More details will be provided on the Lab 3 assignment sheet that will be posted soon.