EE 477 Sec. 34176D, 34444D, 01434511D Assignments

Please note assignments are in reverse order. The newest assignments are at the top.

11/20/03 A revised Lab 3 has been posted. I'm sorry for any inconvenience. I thought it would be helpful if you did not need to do clock generation on-chip, but too many students figured out clever ways of avoiding the design issues I want you to confront. I'm happy that you're all thinking of such great solutions. Let's just put our solutions into the design itself.

11/19/03 details of the project (lab 3) have been posted.

11/12/03 The solution to assignment 6 has been posted. The solution to problem 6 is partial. Note that the increased capacitance added by the diffusion used as interconnect tends to increase the power consumption. So the average power consumption is increased by capacitance and decreased by added resistance, and therefore in this case the only way to determine exactly what happens is through detailed simulations or analysis. All I wanted you to say was that the added resistance and capacitance affected power consumption, one reducing average power, and one increasing it. Also on problem 3 it should say the rise time should be increased.

11/07/03 a description of the project (lab 3) has been posted.

11/04/03 The solution to homework 5 has been posted.

11/04/03 Lab Assignment #2 has been posted. It is due 11/19/2003. I also posted some sample SPICE commands prepared by Dhananjay Raghavan.

11/03/03 Homework Assignment 6 has been posted. It is due 11/11/2003.

10/24/03 Homework Assignment 5 has been posted. It is due 10/30/2003.

10/21/03 I have reposted lab 1 with a couple of changes. Note that the 4-input NAND has unit size PMOS transistors.

10/20/03 Lab 1 has been posted. Note that the entire project description will be posted in a day or two.

10/07/03 The solution to Homework 4 has been posted. Note that in problem 2 Vdsp is > or = -5 v., as well. Also note that in problem 7 the transistor is in the linear region, NOT the saturation region, but that does not affect the answer.

10/04/03 The solution to Homework 3 has been posted.

9/29/03 Homework assignment 4 has been posted. It is due Oct. 7, 2003 at 4 PM. Solutions will be posted at 8 PM.

9/29/03 The solution to homework 2 has been posted.

9/24/03 A flash animation showing the patterning of poly and metal using photoresist is shown here.

9/22/03 Homework Assignment 3 has been posted. It is due 9/29/03 at 4 PM in EEB 300.

9/22/03 The solution to Homework Assignment 1 has been posted.

9/12/03 Homework Assignment 2 has been posted. It is due Sept. 19 at 4 PM in EEB 300.

9/5/03 Homework Assignment 1 has been posted. It is due Sept. 12 at 4 PM in EEB 300.

1/03 Please read Chapter 1 of the text.