University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3

Module Design, IRSIM and SPICE

Laboratory #3 Due December 6, 2002 4:00 PM

This lab addresses the design of a special-purpose circuit. You can use any combination of clocks you wish, since these are inputs to the circuit and you do not have to design them. You should use the cells you designed in labs 1 and 2 to build your circuit. Do not change transistor sizes here. Do not change the circuit structure of your cells. Do not use dynamic logic. However, you can modify the layout if you can see some ways to make the circuits smaller or faster.

The circuit you are to design performs the following function: It reads in a 1-bit value from the single-bit data line for every clock cycle, for 7 cycles. Odd parity is computed for the 7 bits, and the entire 7-bit word and parity bit is output from the circuit on the 8th cycle. On the 8th cycle, the circuit begins inputting the first bit of the second word. You can compute the parity sequentially, as each bit is input, or in parallel once all 7 bits are input.

For this lab, you can use any layout strategy you choose. The goal is to minimize the area·delay (the product of area and delay). Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. Pay close attention to the specific delay you are to measure.

1. (40%) Design your circuit and create a MAGIC layout using the cells you have already designed. The bulk of the work here should be the routing of your design. Include your logic/gate level diagram.

2. (15%) Simulate your layout with IRSIM to ensure that it works logically. Set up the inputs so that the first word input is 0101010, and the second word input is 1011100. The third word is 0000000, and the fourth word is 1111111.

3. (20%) Simulate your circuit with SPICE.

4. (15%) Measure the area of your design in square lambda. The delay is the length of the clock cycle. Compute the area-delay product of your design. Be sure you convert microns to lambda in order to get credit for this part of the lab. This area-delay product will be used for the design contest.

5. (10%) Design creativity: Change your design in any way you like to improve the area-delay product. Explain your changes and give the final area-delay.

Lab Report Contents:

1.Title page

2.Discussion and explanation of how your design works.

3.Block diagram of your design

4.Floorplan (where each cell is on your layout)

5.IRSIM and SPICE outputs for your design.

6.Layout

7.Area-delay product - please compute this product

8. Modified design (see part 5), simulation, explanation, and final area-delay product.