Milestone 4

The proprietary algorithm was given to us by Jabil, thus there was no need to optimize the algorithm however the implementation of the algorithm on hardware was needed to be tested. 

The team ran testbench simulations of the Verilog code to iterate through "window_alg.v" file. The projected result was to generate a synthesized output with quantifiable signal values. Once completed, the results of this test could be used to validate Jabil's implementation of the DFE algorithm.

**The code could not be displayed on this website due to an NDA restriction, however, it is available for distribution to Jabil Electronics**