Task Breakdown and Plan

• Study and understand details of signal transmission for specific DFE use case.

• Create Vivado block design based on provided schematics

• Write an RTL module for a required signal windowing process using SystemVerilog

• Complete and verify simulation by running it on provided Zynq Ultrascale+ ZCU 111 FPGA.

Concepts

Multiple HDL designs will be implemented to achieve the goal of the provided algorithms. However the algorithm used has been already provided to us. We had consider several design timelines. Different components to the timeline include... 

• A Matlab simulation of the algorithm

• An RTL implementation

• hardware verification on FPGA

Concept Selection

The concept selection for RTL algorithm design is disclosed. However our design timeline will be as follows...

create Matlab simulation of the algorithm  --> implement memory mapping RTL design --> Verify hardware design on FPGA by testing JTAG outputs

Analysis

The exact details of our software and hardware designs and function are proprietary, we are using MatLab to run simulations on designs in order to determine how to proceed with application of the DFE algorithms on an FPGA.

Test Plan

We designed an RTL testbench to run analyze our program before moving to hardware implementation. Hardware tests will be designed further on the  Zynq Ultrascale+ ZCU 111 SoC using JTAG inputs and outputs. Time-frequency data inputs will be manipulated in order to achieve the required goal and tested for accuracy. Our final goal is to run a hardware simulation on the FPGA and provide a comprehensive testing platform through the processor on the SoC.