Project
28nm High-K Metal Gate CMOS Development
Major Tasks:
1. Analysis of device mismatch
2. Analysis of device electrical data
3. SPICE model of passive devices
4. Coding of test program
5. Design of experiment and wafer(Lot) handling
Summary
During my employment at TSMC, one of my major tasks is to perform analyses of device mismatch. My main contribution has been the discovery of the relation between metal gate structure and mismatch that I made from the measurement of the electrical characteristics. If the penetration of the formed multi-layer metal gate into the top layer of metal cannot be effectively blocked from piercing through the other metal layers and even getting into the inside of silicon, threshold voltage instability will be caused, thus generating a worse mismatch. This can be further improved by increasing the thickness of the block layer. Nonetheless, if the block layer is too thick, it makes the seal or the subsequent metal layer unable to fill up smoothly. This aforesaid research experience allowed me to be more familiar with the use of the electrical analysis to adjust the semiconductor architecture and deduce a feasible physical model.
Moreover, I participated deeply in the fabrication of advanced 28nm CMOS. Since the fabrication of advanced CMOS involves more processes such as STI, seal spacer, and CMP in comparison to the fabrication of TFT, it has enabled me to gain a more comprehensive understanding of semiconductor fabrication process. Under the mutual cooperation among the colleagues, we made an appropriate adjustment to the fabrication process, which led the yield rate of the fabrication of TSMC’s 28nm CMOS to a considerable increase within a year.