Developing better crystallization methods is another way to improve the quality of TFTs. So my graduate study was focused on “Device Characteristics and Reliability of MILC Poly-Si TFTs”, the goal of which was to study a new crystallization method called MILC which shows better mobility than traditional SPC or as-deposited poly-Si films. To verify the idea experimentally, I used process tools in the clean room facility of National Nano device Laboratories in Taiwan to fabricate MILC devices with a new test structure. Specifically, in addition to the nominal transistor, the proposed structure contains three additional monitor transistors having their own source/drain terminals and the channel directions (from source to drain) of the three monitor transistors (D-MT, C-MT, ad S-MT) are perpendicular to the channel direction of the nominal transistor (As shown in attached file). The study provided a quick and accurate way to assess the quality of the channel and reliability issues of the TFTs.
1. For assessing the channel quality, the electrical measurements of the three monitor transistors can sense the location dependence of the film crystallinity. This is especially important for poly-channel formed by MILC method, since the film crystallinility is closely related to the distance between the seeding window and the film location. The results showed that the position crystallized in the early stage has better quality than the one crystallized latter. The trend is consistent with SEM inspection. Based on the feedback from this method, the impacts of crystallization conditions could be promptly evaluated and amended.
2. For the evaluation of reliability, I focus on spatially resolving the mechanism of hot carrier effects in the MILC channel. In the experiments, the nominal transistor in the test structure is subjected to the stress by applying a high drain voltage and various gate voltages. The resulted damage is location dependent and can be revealed by probing the monitor transistors. For minor stress condition, this scheme successfully shows higher sensitivity than conventional characterization approaches. But the sensitivity is lowered in the case of higher stress condition. It is suspected that the major damage is induced in an offset region not covered by the channel of the monitor transistors. To address this issue, I proposed a new measurement method (As shown in attached file) which had the channel current flowing from the source terminal of one monitor transistor to the drain terminal of the nominal transistor. Since the flow path now flows through the offset region, the damage situation could be revealed, and thus the sensitivity can be properly revealed. This modified scheme also makes the test structure feasible for characterization of TFTs with LDD.