Dr. Santosh Kumar Vishvakarma

Doctor of Philosophy (Ph.D.)

Department of Electronics and Communication Engineering

Indian Institute of Technology Roorkee (IITR), India, 2010

Master of Technology (M.Tech.)

University Center of Instrumentation and Microelectronics (UCIM),

Punjab University Chandigarh, India, 2003

Master of Science (M.Sc)

School of Electronics

DAVV Indore (M. P.) India, 2001

Bachelor of Science (B.Sc)

Faculty of Science, Dept. of Electronics

D. D. U. University Gorakhpur (U.P.) India, 1999

Higher Secondary

M. G. Inter College, Gorakhpur

U. P. Board Allahabad, India, 1996

High School

Indrasana Inter College Balapar, Gorakhpur

U. P. Board Allahabad, India, 1994

My Post Doctoral Work:

Unified 3D Analytical Modeling of Nanoscale Gate-All-Around (GAA) Square Gate (SqG) and Circular Gate (CirG) MOSFETs

During post doctoral tenure, we have developed the 3D analytical model of Square Gate (SqG) and Circular Gate (CirG) gate all around (GAA) MOSFETs for low-doped channel. For these devices we have carried out for the 3D subthreshold electrostatics of low-doped gate-all-around MOSFETs with circular and square cross sections. The model is based on a solution of the 3D Laplace equation utilizing the high symmetry of the devices and assuming near-parabolic potential distributions in the directions perpendicular to the gates for the central regions. To account for short-channel effects, additional functional forms are used near source and drain. High precision is made possible by utilizing auxiliary boundary conditions obtained from a conformal mapping analysis. Combining this model with a long-channel approximation for strong inversion, the drain current in the full range of bias voltages is calculated. The model compares very well with numerical calculations obtained from the ATLAS device simulator.

My Ph.D. Research Work:

Two Dimensional Quantum Mechanical Analytical Potential Modeling of Nanoscale Metal Gate (Hf/AlN_x)/Midgap Symmetric Double Gate MOSFET: A Surface Potential Approach

This part of the research work explores the 2D modeling of potential for nanoscale Double Gate MOSFET with Ultra Thin Body (UTB) structure having intrinsic channel region to model various electric characteristics. Further, using work function engineering, we have proposed a Metal Gate Symmetric Double Gate (MG-SDG) MOSFET with Hafnium (Hf) as a gate metal and Aluminum Nitride (AlN_x) as the buffer layer (See fig. 1 and 2). An analytical expression is modeled to obtain the two dimensional (2D) potential profile using the two dimensional Poisson’s equation with the boundary values based on the physics of the device and parabolic potential profile from front to back gate for Symmetric Double Gate (SDG) MOSFET from the general modeling of center and surface potential expressions. For the post threshold region of operation, centre and surface potentials are modeled from 2D ATLAS simulation. The threshold voltage of the device is evaluated from the consideration of short channel effects (SCEs) and quantum mechanical effect (QME) for the various analyses of other parameters. The analysis is carried out for Midgap Symmetric Double Gate (SDG) MOSFET and MG-SDG MOSFET. Various variations of potential have been carried out for Midgap SDG MOSFET and MG-SDG MOSFET. For the purpose of the validation of our proposed model, the results obtained through our developed model has been compared and contrasted with reported experimental/theoretical results and with 2D ATLAS device simulator.

Inversion Charge Density and Drain Current Modeling of Nanoscale Metal Gate (Hf/AlN_x)/Midgap Symmetric Double Gate MOSFET

This part of research work gives an extensive modeling of inversion charge density and drain current for Midgap and Metal Gate DG devices using our developed surface potential model. Inversion charge density is modeled analytically and numerically with the consideration of one dimensional potential approach. But very few groups have estimated analytical inversion charge using two dimensional approaches. So, it was our motivation for the analytical modeling to have an expression and estimation of the inversion charge density. Quantum and classical analytical inversion charge density is estimated analytically with the surface potential method for the proposed DG devices. Various variations of inversion charge density are carried out for Midgap SDG MOSFET and MG-SDG MOSFET. For the purposes of validation of our model, we have compared the inversion charge density from our proposed analytical model with reported analytical model.

The drain current model is carried out with classical consideration and quantum mechanical approach. In most of drain current models, it has been found that the estimation of drain current is carried out with the calculation of self-consistent potential within the active silicon region. In this work, we have carried out the drain current model from the inversion charge density approach obtained from developed surface potential model. For accurate estimation of inversion charge density and drain current, we have considered the accurate gate capacitance and electron mobility value for nanoscale DG device. Various drain current characteristics are carried out with accurate gate capacitance and mobility values for the accuracy of model.

Modeling of Leakage Currents Associated with Proposed Nanoscale Metal Gate (Hf/AlN_x) Symmetric Double Gate (MG-SDG) MOSFET

As the silicon industry is moving towards the possible end of the roadmap, controlling the variation in device parameters during fabrication becomes a great challenge. With the aggressive scaling of device parameters, various leakage currents increase. Power dissipation both static as well as dynamic in case of CMOS is one of the most important limitations encountered today in the development of high performance circuits and systems. It this part of the research work, we have carried out the modeling and estimation of various leakage current components such as subthreshold current, gate to channel leakage current, edge direct tunneling current and band to band tunneling current and its dependence on various device parameters for Metal Gate Symmetric Double Gate (MG-SDG) MOSFET. The electric field modeling across the insulator layer is carried out through our developed surface potential model.

Latency Minimized MGDG Based SRAM Cell Design: A Device/Circuit Co-Design Approach

In this section, we have developed Metal Gate Double Gate (MGDG) based latency minimized SRAM cell, a device/circuit co-design technique for the generation of low leakage SRAM cell. The estimation of semiconductor capacitance and algorithmic flow for latency minimization is carried out with MGDG based SRAM cell. The estimated latency time with this approach is found to be 1.33 ps. Our analysis shows that use of MGDG devices with intrinsic body reduces latency introduced by body biasing mechanisms for leakage reduction.