SPI -enabled SRAM memory Chip

The SRAM memory design for the implantable pacemaker application consists of several key blocks, including a wordline decoder, SRAM array, I/O circuitry, a parallel-in serial-out (PISO) register, and a serial-in parallel-out (SIPO) register. These blocks work together to facilitate efficient read and write operations. The complete circuit comprises a total of 24 pins, including power and ground connections. 

Process Technology node: 180nm

BRO-PUF

The 16-BRO (Bi-directional Ring Oscillator) PUF is built using tristate inverters, ring oscillators, multiplexers, and comparators. Each 3-stage ring oscillator consists of back-to-back tristate inverters forming a controllable ring structure, enabling selective activation for better power efficiency and isolation. A total of 128 such oscillators are implemented, with their frequency variations—arising from manufacturing process differences—providing the entropy source for the PUF. Two 64×1 multiplexers select one ring oscillator each from two groups of 64, forming a pair whose outputs are compared using a frequency comparator. The comparator identifies the faster oscillator, producing a 1-bit output. By changing the multiplexer inputs, multiple oscillator pairs can be compared, generating a unique multi-bit response vector that serves as the PUF fingerprint. 

Process: 180nm CMOS

ECO-RV

Eco-RV is a compact, energy-efficient, dual-issue RISC-V core designed for AI-centric embedded workloads. It reaches 96.7 MHz, delivers 3.24 CM/MHz on CoreMark, and achieves an Embench score of 1.36. The core consumes 73.58 mW with a power efficiency of 17.96 µW/MHz. Performance is enhanced by a lightweight accelerated datapath built around a configurable CORDIC-based MAC/dot-product unit, with L0 cache with prefetching further improves throughput and reduces off-chip memory access. 

Process: 180nm CMOS

BIO-RV

The BIORV is a 32-bit RISC-V multicycle CPU supporting basic R-type (add, sub), I-type (addi, andi), load/store (lw, sw), branch (beq), and jump (jal) instructions. Its hazard-free, non-pipelined design offers predictable instruction timing, making it ideal for educational purposes, research on RISC-V architecture, and simple embedded control systems such as basic IoT nodes and sensor controllers. Simulated at a standard operating frequency of 50 MHz (20 ns period), it is optimized for low-power, low-performance applications and FPGA/ASIC teaching platforms. 

Process: 180nm CMOS

Digital compute-in-memory

A 16×4 memory using 10T NOR bitcells that perform in-memory multiply–accumulate (MAC) operations. By integrating computation and storage, the design overcomes von Neumann bottlenecks. The bitcells enable both data storage and logic operations, allowing MAC execution directly within the array. Inputs are applied via wordlines, and stored weights enable parallel multiplication, with partial sums accumulated along the bitlines for efficient vector–matrix multiplication. 

Process: 180nm CMOS

Neural Processing Engine

A dual 8-bit Multiply-Accumulate (MAC) unit. It is used for efficient parallel computation of two independent MAC operations. The outputs of the two MAC blocks are packed and serialized using a Parallel-In Serial-Out (PISO) register, and finally processed through an Arithmetic Function (AF) block to produce an 8-bit output. This design is aimed at supporting arithmetic-heavy workloads such as signal processing, lightweight neural computation, and embedded control systems. The novelty of this design lies in the optimization of the neuron architecture by eliminating one Arithmetic Function (AF) block. By sharing a single AF unit for both MAC paths, the design reduces resource utilization and area overhead, while also improving overall computational efficiency and speed—making it ideal for resource-constrained and high-throughput applications.

Process: 180nm CMOS

8 - Kb SRAM

A 8Kb SRAM chip prototype developed to evaluate and verify performance and functional correctness in silicon. The objective is to validate read/write stability, leakage behavior, access time, and overall robustness across process corners, voltage, and temperature variations. This prototype represents a key step toward integrating a reliable low-power memory block into a medically critical application.

Process: 180nm CMOS

Compute-in-memory macro

It is a digital compute-in-memory design developed for edge AI applications, consisting of a wordline decoder, SRAM array, adder tree, and I/O circuitry that collectively perform efficient multiply-accumulate (MAC) operations, making it well-suited for Edge AI, IoT, and neural network-based applications. 

Process: 180nm CMOS

8 - Kb SRAM CIM

This 8 Kb SRAM Compute-in-Memory (CIM) prototype incorporates peripheral compute-in-memory to evaluate performance and functional correctness in silicon. By performing computations directly within the memory macro, it reduces data movement, enhancing energy efficiency and speed for data-intensive tasks. The design demonstrates the feasibility of integrating computation and memory in a single macro, assessing stability, energy efficiency, and functionality under varying operating conditions.

Process: 180nm CMOS

CORX

CORX is a CORDIC-based eXecution Engine designed to compute essential AI operations including Multiply-Accumulate (MAC), Sigmoid, Tanh, Softmax, and ReLU. The core uses a 16-stage pipelined architecture implemented in Verilog HDL (IEEE 2001) using fixed-point Q1.15 arithmetic. The design eliminates traditional multipliers and dividers by utilizing a shift-add approach inherent to CORDIC algorithms, enabling efficient computation of trigonometric and hyperbolic functions. The core was developed for low-power AI inference tasks and taped out using SCL 180nm CMOS technology.

Process: 180nm CMOS

SoC for IoT WSN

Technology: AMS 180nm