Conference Papers
Conference: (81)
2024(01)
81. R. Sharma, N. S. Dhakad, G. S. Reddy, V. Sharma and S. K. Vishvakarma, "ReCAM: Resistive RAM Digital Content Addressable Memory Using Novel 3T1R Bitcell," 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3, doi: 10.1109/EDTM58488.2024.10511788.[PDF].
2023 (02)
80. Sudheer Vishwakarma, Gopal Raut, Narendra Singh Dhakad, Santosh Kumar Vishvakarma, Dhruva Ghai, "A Configurable Activation Function for Variable Bit-Precision in Hardware DNN Implementation," 6th IFIP International Internet of Things Conference, IFIP-IoT 2023.
79. Sakib Ansari, Kavitha S, Santosh Vishvakarma and Bhupendra Reniwal, “Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application”, International Conference on VLSI Design (VLSID), January 2023, Hyderabad, India. [PDF]
2022 (06)
78. Nikhil Rangarajan, Gopal Raut, Santosh Vishvakarma et al. "SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture." In 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, 2022, Nicosia, Cyprus. [PDF]
77. Ravi Kumar, Rajasekhar Nagulapalli, S K Vishvakarma, “A Novel Gain Enhanced Folded Cascode OPAMP in 28nm CMOS technology”, International Conference on Electrical, Computer and Energy Technologies (ICECET 2022) 20-22 July 2022, Prague-Czech Republic. [PDF]
76. Ravi Kumar, Rajasekhar Nagulapalli, Rushikesh Hake, S K Vishvakarma, “A Low-Power 2-to-7 Modulus Programmable Prescaler with 50% Output Duty Cycle”, Proc. of the International Conference on Electrical, Computer and Energy Technologies (ICECET 2022) July 2022, Prague-Czech Republic. [PDF]
75. Kavitha S, S. K. Vishwakarma, and B. S. Renewal, “An Approach towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array”, 26th International Symposium on VLSI Design and Test (VDAT-2022), July 2022.
74. Varun Bhatnagar, Gopal Raut, Santosh Kumar Vishvakarma, “Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array”, Proceedings of the Great Lakes Symposium on VLSI, June 2022. [PDF]
73. Kavitha S, B. S. Reniwal and S. K. Vishwakarma “Enabling In-Memory Computing with New Energy Efficient Assist Sense Amplifier for Boolean Computation in SRAM Array," IEEE 35th International Conference on VLSI Design, VLSID-2022, Feb 2022.
2021 (02)
72. Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma and Patrick Girard, "Voltage Bootstrapped Schmitt Trigger-based Radiation Hardened Latch design for Reliable Circuits", GLSVLSI 2021. [PDF]
71. Mythrai, Pragna, Kavitha S, B. S. Reniwal and S. K. Vishwakarma, “Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation," IEEE 25th International Symposium on VLSI Design and Test (VDAT), 2021. [PDF]
70. Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh K Vishvakarma, J Soumya, MB Srinivas, Phaneendra K Yalavarthy, Abhinav Kumar, V Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi, "Object Classification Technique for mmWave FMCW Radars using Range-FFT Features", International Conference on COMmunication Systems & NETworkS (COMSNETS), pp. 111-115. [PDF]
2020 (02)
69. Raut, Gopal, Shubham Rai, Santosh Kumar Vishvakarma, and Akash Kumar, "A CORDIC based Configurable Activation Function for ANN Applications", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 78-83, 2020. (Nominee for Best Paper Award) [PDF]
68. Linga Reddy Cenkeramaddi, Jyoti Bhatia, Ajit Jha, Santosh Kumar Vishkarma and Soumya J, "A Survey on Sensors for Autonomous Systems", 15th IEEE Conference on Industrial Electronics and Applications (ICIEA2020), 21-25 June 2020, Kristiansand, Norway. [PDF]
2019 (01)
67. Gunjan Rajput, Gopal Raut, Sajid Khan, Neha Gupta, Santosh Kumar Vishvakarma, “ASIC Implementation of Biological Inspired Spiking Neural Network”, Conference ICETET (ICETET-2019). [PDF]
2018 (06)
66. Kuldeep Raghuwanshi, Prachi Sanvale, Vaibhav Neema, Ambika Prasad Shah and Santosh Kumar Vishvakarma, “Vth Extraction based Run Time Transistor Width Oversizing (TWOS) Module for On-chip NBTI Mitigation”, 15th IEEE India Council International Conference (INDICON-2018), December 16-18, 2018. [PDF]
65. Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana and Santosh Kumar Vishvakarma, “A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design”, 22nd Symposium on VLSI Design and Test, Madurai, India June 28-30, 2018. [PDF]
64. Jai Gopal Pandey, Mausam Nayak, Tarun Goel, Chhavi Mitharwal, Sajid Khan, Santosh Kumar Vishvakarma, Abhijit Karmakar and Raj Singh, “A VLSI Architecture for PRESENT Lightweight Cipher with FPGA and ASIC Implementations”, 22nd Symposium on VLSI Design and Test, Madurai, India June 28-30, 2018.
63. Japa Aditya, T. Nagateja, Santosh Kumar Vishvakarma, Palagani Yellappa, Jun Rim Choi, and Ramesh Vaddi, "Tunneling Field-Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities", 2018 International Symposium on Circuits and Systems (ISCAS)-2018, Florence, Italy, May 27-30, 2018.
62. Bhupendra Reniwal and S. K. Vishvakarma, " Variability Aware Design of Energy Efficient SRAM in Conventional & Non-Conventional MOS Technologies: A Sense Amplifier Perspective" 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, Pune, India, Jan 8-10, 2018.
61. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar and S. K. Vishvakarma, "On-Chip NBTI Sensor Circuits for Stable and Reliable CMOS Circuits, "31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, Pune, India, Jan 8-10, 2018.
2017 (08)
60. Garima Shukla, Abhishek Kumar Upadhyay and S.K.Vishvakarma, " Effect of Back Gate Voltage on Double Gate Single Layer Graphene Field-Effect Transistor with Improved ION," 19th International Workshop on Physics of Semiconductor Devices (IWPSD), SSPL Delhi & IIT Delhi, Dec. 2017.
59. Abhishek Upadhyay, Ajay Kushwaha and S.K.Vishvakarma, "Modified Quasi Ballistic Transport Model for Graphene FET Simulation," 19th International Workshop on Physics of Semiconductor Devices (IWPSD), SSPL Delhi & IIT Delhi, Dec. 2017.
58. Pooja Bohara and S.K.Vishvakarma, "Independent Gate Operation of NAND Flash Memory Device with Improved Retention Characteristics," 19th International Workshop on Physics of Semiconductor Devices (IWPSD), SSPL Delhi & IIT Delhi, Dec. 2017.
57. Ankur Beohar, Ambika Prasad Shah, Nandakishor Yadav, and Santosh Kumar Vishvakarma, "Design of 3D Cylindrical GAA-TFET Based on Germanium Source with Drain Underlap for Low Power Applications,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2017) at National Tsing Hua University, Hsinchu, Taiwan, October 18th to 20th, 2017.
56. Nandakishor Yadav, Ambika Prasad Shah, Ankur Beohar and Santosh Kumar Vishvakarma, “Source Drain Gaussian Doping Profile Analysis for High ON Current of InGaAs Based HEMT, " IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2017) at National Tsing Hua University, Hsinchu, Taiwan, October 18th to 20th, 2017.
55. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar and Santosh Kumar Vishvakarma, "Subthreshold Darlington Pair Based NBTI Sensor for Reliable CMOS Circuits, " IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2017) at National Tsing Hua University, Hsinchu, Taiwan, October 18th to 20th, 2017.
54. Pooran Singh, Bhupendra Reniwal, Vikas Vijayargiya, Vishal Sharma and S. K.Vishvakarma, "A 9T SRAM for ultra-low power applications", 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 7th-11th Jan 2017, Hyderabad, India.
53. Bhupendra Reniwal, Pooran Singh, Vikas Vijayvargiya and S. K. Vishvakarma, "A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM", 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 7th-11th Jan 2017, Hyderabad, India.
2016 (07)
52. Nandakishor Yadav, Ankur Beohar and S. K. Vishvakarma, "Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k spacer FinFET," IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), December 19-21, Gwalior, India.
51. Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya and S. K. Vishvakarma, "Investigation of DC Characteristic on DG-Tunnel FET with high-K Dielectric Using Distinct Device Parameter," IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), December 19-21, Gwalior, India.
50. Tuhina Bhalla, Mahesh Kumawat, Atul Awadhiya, S.K. Vishvakarma, Vaibhav Neema, “Energy Efficient Low Power DC Balanced Full Custom Circuit Design of 8b/10b Encoder and Decoder ”, 3rd IEEE International Conference on Microelectronics, Circuits and Systems (Micro2016), 9th-10th July 2016, Kolkata, India.
49. Atul Awadhiya, Maisagalla Gopal, Tuhina Bhalla, S.K. Vishvakarma, Vaibhav Neema, “Performance Analysis of SiC S/D with Symmetric Dual-k Spacer n-FinFET”, 3rd IEEE International Conference on Microelectronics, Circuits and Systems (Micro2016), 9th-10th July 2016, Kolkata, India.
48. S. Mishra, M. Santhakumar, S.K. Vishvakarma, “Task space motion control of a mobile manipulator using a nonlinear PID control along with an uncertainty estimator” in International Conference on Advancements in Automation Robotics & Sensing ICAARS, Coimbatore, India, June 23-24, 2016
47. B. S. Reniwal, S. K. Vishvakarma and D. Dwivedi, "Variability Resilient, Low Energy Differential Current Compensation Based Sense Amplifier for Robust SRAM", 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 4th-8th Jan 2016, Kolkata, India (Best Paper Award).
46. Garima Shukla, Abhishek Kumar Upadhyay and S.K.Vishvakarma, “Improved Critical Electric Field and Saturation Current in Double Gate Single Layer Graphene Field-effect Transistor With Back-gate Voltage Effect”, International Conference On Recent Innovations in Electrical, Electronics, Computer, Information, Communication, and Mechanical Engineering – ICRIEECICME-2016, Feb.19, New Delhi.
2015 (12)
45. S. K. Vishvakarma, B. S. Reniwal, V. Sharma, C. B. Kushwah, D. Dwivedi, “Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity", IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), December 21st-23rd, 2015, Indore, India.
44. M. Gopal and S. K. Vishvakarma, “Effect of Asymmetric Doping on Asymmetric underlap Dual-k Spacer FinFET”, 12th IEEE India International Conference (INDICON-) on Electronics, Energy, Environment, Communications, computer and Control, 17th- 20th December 2015, New Delhi.
43. Neha Jagwani, Santosh Kumar Vishvakarma and Vikas Vijayvargiya, “Effect of Gate and Channel Engineering on Digital Performance Parameters using Tied (3T) and Independent (4T) Double-Gate MOSFETs, IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), December 21st-23rd, 2015, Indore, India.
42. Ankur Beohar, Santosh Kumar Vishvakarma, " Performance Enhancement of 3D Cylindrical (Cyl) Gate All Around (GAA) Tunnel Field-Effect Transistor (TFET) With Asymmetrical Spacer Width" 18th International Workshop on Physics of Semiconductor Devices (IWPSD), IISc, Bangalore, Dec. 7-10, 2015, Bangalore, India.
41. Deepika Gupta and Santosh K. Vishvakarma, "A New Approach to Suppress GIDL in NAND Flash Memory",18th International Workshop on Physics of Semiconductor Devices (IWPSD), IISc, Bangalore, Dec. 7-10, 2015, Bangalore, India.
40. Gaurav Singh, Vikas Vijayvargiya and, S.K. Vishvakarma, "Investigation of Underlap and Spacer Engineering in Multigate-MOSFET for Improved Short Channel Characteristics at 14 nm",18th International Workshop on Physics of Semiconductor Devices (IWPSD), IISc, Bangalore, Dec. 7-10, 2015, Bangalore, India.
39. Mansimaran Kaur, Deepika Gupta, Vikas Vijayargiya, Santosh Vishvakarma, Vaibhav Neema, "Characterization of BE-SONOS Flash Memory using Rare Earth Materials in Tunnel Barrier with improved memory dynamics”, IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), 27th-29th, November 2015, Hyderabad, India.
38. Dheeraj Sharma and Santosh Vishvakarma, “Investigation of unified approach for the development of analytical potential model for Quadruple, Square and Cylindrical Gate, Gate-All-Around MOSDETs,” IEEE International Conference on Research in Computational Intelligence and Communications Networks (ICRICN 2015), November 20-22, 2015, Kolkata, India.
37. Praneet Bhatia, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma, "An Offset-Tolerant SelfCorrecting Sense Amplifier for Robust High-Speed SRAM", 19th International Symposium on VLSI Design and Test (VDAT), June 26-29, 2015, Ahmedabad, India.
36. Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma and Devesh Dwivedi, " Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET", 25th Great Lakes Symposium on VLSI (GLSVLSI), May 20-22 2015, Pittsburgh, PA, USA.
35. Chandrabhan Kushwah, S. K. Vishvakarma and Devesh Dwivedi, " Stability Analysis of Single-Ended Boost-Less Sub-threshold 7T FinFET SRAM Cell under Process-Voltage-Temperature Variations", 16th International Symposium on Quality Electronic Design (ISQED 2015), March 2-4, 2015, pp. 18-22, Santa Clara, CA, USA.
34. GSR Srivatsava, Pooran Singh, Siddharth Gaggar and S. K. Vishvakarma, “Dynamic power reduction through clock gating technique for low power memory applications,” IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT-2015), 5-7 March 2015, Coimbatore, Tamilnadu, India.
2014 (05)
33. Anupreet Gupta, Hajra Anwer, Deepika Gupta, Vikas Vijayvargiya and Santosh Kumar Vishvakarma, “A Non- Volatile Memory MONOS Device for Improved Stability Applications,” IEEE International Conference on Devices, Circuits and Communications (ICDCCom), 12th-13th Sept. 2014, BITS Rachi, India.
32. Chandrabhan Kushwah and S. K. Vishvakarma, " A Sub-threshold Eight Transistor (8T) SRAM Cell Design for Stability Improvement", IEEE International Conference on Integrated Circuit and Technology (ICICDT)-2014, 28th-30th May 2014, Austin, Texas, USA.
31. Chandrabhan Kushwah, S. K. Vishvakarma, D. Dwivedi" Single-Ended Sub-Threshold FinFET 7T SRAM Cell Without Boosted Supply", IEEE International Conference on Integrated Circuit and Technology (ICICDT)-2014, 28th-30th May 2014, Austin, Texas, USA.
30. Pooran Singh and S. K. Vishvakarma, "Design of high-speed DDR SDRAM controller with less logic utilization", 2nd IEEE International Conference on Devices, Circuits and Systems - ICDCS 2014, 6-8 March, 2014, Coimbatore, Tamilnadu, India.
29. Anupreet Gupta, Hajra Anwer, B. S. Reniwal & S. K. Vishvakarma, “Analysis of Stability Issues and Power Efficiency of Symmetric and Asymmetric Low Power Nanoscaled SRAM Cells”, 2nd IEEE International Conference on Devices, Circuits and Systems - ICDCS 2014, 6-8 March 2014, Coimbatore, Tamilnadu, India.
2013 (08)
28. Dheeraj Sharma, S. K. Vishvakarma and Devesh Dwivedi “Analyses of scaling effects on analog/RF performance of nanowire gate-all-around MOSFET”, in Proc. ICLDC Dec. 3, 2013, IBM Bangalore.
27. B. S. Reniwal, S. K. Vishvakarma and Devesh Dwivedi, “Robust Ultra-Fast Data Sensing Technique for Low Power Asymmetrical SRAM with Self-Shut-Off Feature”, IEEE Asia Pacific Conference on Post Graduate Research in Microelectronics & Electronics, (Prime Asia -2013), Dec 19-21, 2013, India.
26. Vikas Vijaywargiya and S.K.Vishvakarma, "Effect of Parasitic Capacitance on DG-HGTFET and its influence on Device RF Performance", 17th International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 10-13, 2013, India.
25. Jhalak Patel, Bala Gangadhar J, S.K.Vishvakarma, Pooran Singh, "HW/SW Co-design based Real-Time Face Recognition", IEEE 15th International Conference on Advanced Computing Technology (ICACT-2013), Aug. 10th-11th, 2013 AP, India.
24. Chandrabhan Kushwah and S. K. Vishvakarma, "Sub-Threshold 8T SRAM Cell Immune to Process Variations at ULV Supply", IEEE International Conference on Electron Devices and Solid-State Circuits, June 2nd-5th 2013, Hong Kong.
23. Pooran Singh and S. K. Vishvakarma, "RTL Level Implementation of High-Speed Low Power Viterbi encoder and decoder", IEEE 3rd International Conference on Information Science and Technology (ICIST-2013), March 23rd-25th, 2013 pp. 345-349, Yangzhou, Jiangsu, China.
22. Vikas Vijaywargiya and S. K. Vishvakarma, "Effect of Doping Profile on Tunneling Field Effect Transistor", 9th IEEE Spanish Conference on Electron Devices, February 12th-14th, pp. 195-198, Feb. 2013, Valladolid, Spain.
21. Dheeraj Sharma and S.K.Vishvakarma, "Analysis of Crossover Point and Threshold Voltage for Triple Gate MOSFET", 9th IEEE Spanish Conference on Electron Devices, February, 12th-14th Feb. pp. 99-102, 2013, Valladolid, Spain.
2012 (02)
20. Dheeraj Sharma and S.K.Vishvakarma, "Isomorphic Polynomial based Precise Analytical Modeling of 3D Potential Distribution for Surrounding Gate Gate-All-Around MOSFET", IEEE International Conference on Emerging Electronics (ICEE), Dec. 15th-17th, 2012, IIT Bombay, India.
19. Tor. A. Fjeldly, U. Monga and S. K. Vishvakarma, "Compact Unified modeling of Multigate MOSFETs based on Isomorphic modeling functions", 8th, IEEE, International Caribbean Conference on Devices, Circuits and Systems-2012 (ICCDCS-2012), March 14th-17th, 2012, Playa del Carmen, Mexico (Invited Paper).
2011 (01)
18. Dheeraj Sharma and S. K. Vishvakarma, “Analytical Modeling of the Subthreshold Potential of Nanoscale GAA Rectangular Gate MOSFET”, IEEE International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2011, IIT Kanpur, India.
2010 (03)
17. S. K. Vishvakarma, Udit Monga and Tor. A. Fjeldly, “Unified Analytical Modeling of GAA Nanoscale MOSFETs”, IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 1st-4th Nov 2010 (Invited paper).
16. S. K. Vishvakarma, Udit Monga and Tor. A. Fjeldly, “Analytical Modeling of the Subthreshold Electrostatics of Nanoscale GAA Square Gate MOSFETs”, Proc. NSTI Nanotech Conference, Workshop on Compact Modeling, pp, 789-792, Anaheim, California, USA, June 21st – 25th, 2010
15. B. Raj, S.K. Vishwakarma, A.K. Saxena, S. Dasgupta, “Modeling and Simulation for Double Gate FinFET Device at 30 nm Technology”, Nanotech-2010, Workshop on Compact Modeling, Anaheim, California, USA, June 21st – 25th, 2010.
2009 (03)
14. S. K. Vishvakarma, A. K. Saxena, S. Dasgupta and Tor. A. Fjeldly, “Modeling of Subthreshold Leakage Current for Nanoscale Dual Metal Gate (Hf/AlNx) Double Gate MOSFET,” International Workshop on the Physics of Semiconductor Devices (IWPSD)-2009, December 15th -19th, 2009, Delhi, India.
13. S. K. Vishvakarma, A. K. Saxena, S. Dasgupta, Tor. A. Fjeldly, “Analytical Modeling of Double Gate MOSFET using Back Gate Insulator Thickness Variation”, 2nd IEEE, International Workshop on Electron Devices and Semiconductor Technology (IEDST-2009), June 1-2, 2009, IIT Mumbai, India.
12. Udit Monga, Tor. A. Fjeldly and S. K. Vishvakarma, “Modeling of Quantum Mechanical Effects in Ultra-Thin Body Nanoscale Double-Gate FinFET,” 2nd IEEE, International Workshop on Electron Devices and Semiconductor Technology (IEDST-2009), June 1-2, 2009, IIT Mumbai, India.
2008 (01)
11. V. Komal, S. K. Vishvakarma, R. C. Joshi, A. K. Saxena and S. Dasgupta, “Leakage Optimization for Nanoscale MGDG MOSFET using Dual Metal (Hf/HfN) Gates with AlNx Buffer Layer,” 12th IEEE, VLSI Design and Test Symposium, (VDAT-2008), July, 23-26, 2008, Bangalore, India.
2007 (10)
10. S. K. Vishvakarma, B. Raj, R. Singh, C.R. Panda, A. K. Saxena and S. Dasgupta, “Analytical modeling of threshold voltage for Nanoscale Symmetric Double Gate (SDG) MOSFET with Ultra-Thin Body (UTB)", International Workshop on the Physics of Semiconductor Devices (IWPSD)-2009, December 16th -20th, 2007, pp. 277 - 280, IITB, Mumbai, India.
9. S. K. Vishvakarma, B. Raj, A. K. Saxena and S. Dasgupta, “Evaluation of Eigen Function and Inversion Layer Centroid of Nanoscale Symmetric Double Gate (SDG) MOSFET,” Workshop on Frontier in Electronics (WOFE -07), Mexico, USA, 15th -17th, p. 60, Dec. 2007.
8. S. K. Vishvakarma, B. Raj, A. K. Saxena and S. Dasgupta, “Analytical Drain Current Modeling of Nanoscale Symmetric Double Gate (SDG) MOSFET with Ultra-Thin Body (UTB),” International Conference on Information and Communication Technology (IICT-2007), DIT, Deharadun, India, 26th -28th, July 2007.
7. B. Raj, S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Quantum drain Current modeling of 30 nm Double gate FinFet Device,” Workshop on Frontier in Electronics (WOFE -07), Mexico, USA, 15th -17th, p. 59, Dec. 2007.
6. B. Raj, S. K. Vishvakarma, A. K. Saxena and S. Dasgupta. “Optimum Decoder Design Techniques for Low Power and High-Speed Nanoscale Memories”, International Conference on Modeling and Simulation (CITICOMS-2007), Coimbatore Institute of Technology, 27th -29th, August 2007, India.
5. B. Raj, S. K.Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Potential Modeling of Nanoscale Double-Gate FinFET Device: A quantum mechanical approach,” International Conference of VLSI (IC-VLSI), Valamal Engineering College Chennai, India.
4. B. Raj, S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Threshold Voltage Quantum Mechanical Modeling of Double Gate FinFet Device,” International Conference of Soft Computing and Intelligent Systems, 27th -29th, Dec. 2007, Jabalpur Engineering College, Jabalpur, India.
3. S. K. Vishvakarma, B. Raj, A. K. Saxena and S. Dasgupta, “Two-dimensional Analytical Modeling of Nanoscale Symmetric Double Gate (SDG) MOSFET with Ultra-Thin Body (UTB),” IMS Conference on “Trends in VLSI and Embedded System”, PEC, Chandigarh, India, pp.47-51, 17th -18th, August 2007.
2. B. Raj, S. K.Vishvakarma, A. K. Saxena and S. Dasgupta, “Techniques for Low Power SRAM Design,” National Conference on Design Techniques for Modern Electronic Devices, VLSI & Communication Systems, NIT Hamirpur, India, pp. 55-61, 14th -15th, May, 2007.
1. B. Raj, S. K.Vishvakarma, A. K. Saxena and S. Dasgupta. “Low Power and High-Performance Decoder for Nanoscale SRAM Design,” National Conference on "Trends and Developments in VLSI and Embedded System", Tamilnadu, India, 5th – 6th, March 2007.