PhD Students
Ph.D. awarded from the group (18)
Ph.D. Thesis Title: Design Exploration and VLSI Implementation of Deep Neural Network Accelerator with Configurable Architecture
Internship/Award:
Received ASA Program, Germany fellowship at TU Dresden, Germany.
Received HiPEAC fellowship at TU Dresden, Germany
Graduation: September 2022
Present Affiliation: Knowledge Associate at Centre for Development of Advanced Computing (CDAC), Bangalore, India
Dr. Gunjan Rajpoot
Ph.D. Thesis Title: Hardware Implementation of an Efficient Deep Neural Network for Biomedical Applications
Internship: Ph.D. Research Intern at NXP Semiconductors from July 2019 to June 2020.
Graduation: December 2021
Ph.D. Thesis Title: Performance Assessment of Scaled Charge Trap Flash Memory for Improved Reliability
Internship: Ph.D. Research Intern at NXP Semiconductors from July 2019 to June 2020.
Graduation: July 2021
Present Affiliation: PDK Circuit Simulation QA Engineer at Intel Corporation, Bangalore, India.
Ph.D. Thesis Title: Design Techniques for Radiation Hardened, Reliable and Low Power Circuits
Graduation: June 2021
Present Affiliation: FPGA Design Engineer at BitMapper Integration Technologies Pvt. Ltd., Pune.
Co-supervisor: Dr. Jai Gopal Pandey, CSIR-CEERI, Pilani, Rajasthan, India
Ph.D. Thesis Title: Low Power Secure Circuits and their Design Techniques for Internet of Things
Internship: Ph.D. Research Intern at INTEL, Bangalore from Sept 2019 to June 2020.
Graduation: June 2021
Present Affiliation: SoC Design Engineer at Intel Corporation, Bangalore, India.
Ph.D. Thesis Title: On-Chip Circuit Design Techniques for High-Speed Serial Links
Graduation: May 2020
Present Affiliation: Assistant Professor at Bennett University, Greater Noida, India.
Co-supervisor: Dr. M. Santhakumar, Associate Professor, Mechanical Engineering, IIT Palakkad
Ph.D. Thesis Title: Investigations on Robust Motion Control Designs for Mobile Manipulators
Graduation: May 2020
Ph.D. Thesis Title: High Stable, Low-Power and Error Tolerant SRAM Memory Design for Wireless Sensor Nodes and FPGA
Graduation: July 2019
Present Affiliation: SoC Design Engineer at Intel Corporation, Bangalore, India.
Past Affiliation: Post Doc Research Fellow at NTU Singapore.
Senior R&D Engineer, Synopsys Bangalore, India Pvt. Ltd.
Ph.D. Thesis Title: Compact Modeling of Graphene Field-Effect Transistors for RF Circuit Applications
Graduation: July 2019
Present Affiliation: Scientific Staff at Technische Universität Dresden
Ph.D. Thesis Title: Performance Enhancement of CMOS Digital Circuits using Strain Engineered Asymmetric Dual-k Spacer FinFETs
Graduation: May 2019
Present Affiliation: Associate Professor at Sumathi Reddy Institute of Technology for Women, Telangana.
Ph.D. Thesis Title: Design Techniques for Bias Temperature Instability Aware and Soft-Error Resilient Nanoscale Circuits
Graduation: April 2019
Present Affiliation: Assistant Professor and Associate Dean Corporate Relations at Indian Institute of Technology (IIT) Jammu, India.
Ph.D. Thesis Title: Performance Enhancement of 3D Cylindrical Gate-all-around Tunnel FET and Its Applications for Ultra Low Power Cross Coupled Voltage Doubler Circuit Design
Graduation: Jan 2019
Present Affiliation: Assistant Professor at VIT Bhopal, India.
Ph.D. Thesis Title: Ultra low power, high-stability robust SRAM design for FPGA, image processing, and IoT applications
Graduation: Feb 2018
Present Affiliation: Assistant Professor at Mahindra University Hyderabad, India.
Past Affiliation: SoC Design Engineer, Intel Penang, Malaysia.
Ph.D. Thesis Title: Analysis of Charge Trap NAND Flash Memory for Improved Reliability
Graduation: Sept 2017
Present Affiliation: Assistant Professor at IIIT-Naya Raipur, India.
Co-supervisor: Dr. Devesh Dwivedi, SRAM Development, System Design Group, IBM Bangalore, India (Now as an Associate Director, ASIC, GlobalFoundries, Bangalore, India)
Ph.D. Thesis Title: Variability-Aware Design of SRAM in Conventional & Non-Conventional MOS Technologies: A Sense Amplifier Prospective
Award: Recipient of Best Research Paper Award in "User Track" in VLSI Design Conference-2016.
Graduation: May 2017
Present Affiliation: Assistant Professor at IIT Jodhpur, India.
Past Affiliation: Assistant Professor at IIIT Kancheepuram, India.
Senior Product Development Engineer, UST Global, Bangalore.
Mixed-Signal IP Solution Engineer, Intel Corporation Malaysiya.
Assistant Professor, BITS Pilani, K. K. Birla Goa Campus, India.
Ph.D. Thesis Title: Investigation of Drain Extension Feature in a Double Date Silicon based Tunnel FET for Low Power SoC Applications
Graduation: October 2015
Present Affiliation: Assistant Professor at VIT Vellore, India.
Co-supervisor: Dr. Devesh Dwivedi, SRAM Development, System Design Group, IBM Bangalore, India (Now as an Associate Director, ASIC, GlobalFoundries, Bangalore, India)
Ph.D. Thesis Title: Ultra Low Power SRAM Design in Nanoscale CMOS and Multigate FinFET Technologies
Internship/Award:
Ph.D. intern in SRAM Development, System Design Group, IBM Bangalore for six months from Jan 2013-July 2013.
Recipient of IBM Ph.D. Fellowship Award 2014-15.
Graduation: June 2015
Present Affiliation: Postdoctoral Researcher Associate at the University of Bath, United Kingdom (UK)
Late Dr. Dheeraj Sharma
Ph.D. Thesis Title: Modeling and Analysis of Quadruple and Cylindrical Gate gate-all-around MOSFETs
Internship/Award:
Ph.D. intern in 2013 with Dr. Devesh Dwivedi, SRAM Development, System and Technology Group, IBM, Bangalore.
Recipient of IBM Ph.D. Fellowship Award 2013-14.
Graduation: March 2014
Past Affiliation: Assistant Professor at National Institute of Technology Goa, India.
Assistant Professor, IIITDM Jabalpur, India