Publications

Rohit Sharma and Atul Kumar Nishad, "Performance Evaluation of AsF5-intercalated Top Contact Multilayer Graphene Nanoribbons for Deeply Scaled Interconnects," in High-Speed and Lower Power Technologies, Choi Jung Han, Iniewski Krzysztof (Eds), CRC Press, 2017.
Rohit Sharma and Kiyoung Choi, “Emerging Interconnect Technologies for 3D Networks-on-Chip,” in Design of 3D Integrated Circuits and Systems, Rohit Sharma and Krzysztof Iniewski (Eds.), CRC Press, 2014.
Rohit Sharma, Rajarshi Saha and Paul Kohl, “Low-Loss,High-Performance Chip-to-Chip Electrical Connectivity using Air-Clad Copper Interconnects,” in High-speed Photonics Interconnects, Lukas Chrostowski and Krzysztof Iniewski (Eds.), CRC Press, 2013.

Indian patent granted: “An embedded system for analysis of microstrip-like interconnects”, (Patent no. 319102), 2019.
Indian patent granted: “Trolley System, Device and Method for Controlling Navigation of the Trolley System”, (Patent no. 531011), 2024.
Indian patent granted: “A three-dimensional folded capacitive crossbar array system” (Patent No: 565891), 2024.
US patent application titled “Voltage Regulator” (Patent No: 63/648,449), 2024.
Indian patent application titled “Drafting patent application for Sensor-based, economical Hand Hygiene Prompt device for use in the Open bay design ICUs: HHP-OICU”, 2025.

Theme 1: High-Speed Interconnect Modeling & Signal/Power Integrity

Rohit Sharma et al., "Benchmarking and Reproducibility in Computational and Experimental Characterization of Electronic Packages for Signal/Power Integrity: Four benchmarks serve as standardized cases," IEEE Antennas and Propagation Magazine, vol. 67, no. 2, pp. 51-63, 2025.
Rahul Kumar, Amit Kumar, Surila Guglani, Somesh Kumar, Sourajeet Roy, Brajesh Kumar Kaushik, Rohit Sharma, Ramachandra Achar, “A Temperature and Dielectric Roughness-aware Matrix Rational Approximation Model for the Reliability Assessment of Copper-Graphene Hybrid On-Chip Interconnects”, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 9, pp. 1454-1465, 2020.
S. Kumar, S. Pathania, and R. Sharma, "Investigating the role of sidewall surface roughness on the performance of through silicon vias," IEEE 19th Electronics Packaging Technology Conference (EPTC), Singapore, 2017. 🏆 Awarded Best Paper

Theme 2: Advanced Semiconductor Packaging & Heterogeneous Integration

M. Swaminathan, R. R. Khorasani, I. Partin-Vaisband, R. Sharma, and S. Kumar, "Integrated Vertical Power Delivery – Review & Challenges," IEEE Transactions on Components, Packaging and Manufacturing Technology, 2026.
Somesh Kumar and Rohit Sharma, “Chip-to-Chip Copper Interconnects with Rough Surfaces: Analytical models for Parameter Extraction and Performance Evaluation”, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 2, pp. 286-299, Feb. 2018.
Pradyot Yadav, Rohit Sharma, Madhavan Swaminathan, and Tomás Palacios, "Heterogeneous Integration of GaN and Si CMOS for W-Band 3D Integrated RF Front Ends," SRC CHIMES Annual Review, State College, PA, USA, 2023. 🏆Awarded Best Poster

Theme 3: Graphene & 2D Material-Based Nanoelectronics

Bhawana Kumari, Manodipan Sahoo, and Rohit Sharma, "Electro-Thermal Modeling and Reliability Analysis of Cu-Carbon Hybrid Interconnects for Beyond-CMOS Computing," Applied Physics Letters, vol. 121, no. 10, pp. 101901-6, 2022.
Atul Kumar Nishad and Rohit Sharma, “Analytical Time Domain Models for Performance Optimization of Multilayer GNR Interconnects”, IEEE Journal of Selected Topics in Quantum Electronics, vol. 20, no. 1, 2014.
V. K. Nishad, A. K. Nishad, S. Roy, B. K. Kaushik, and R. Sharma, "First Principle Analysis of Os-passivated Armchair Graphene Nanoribbons for Nanoscale Interconnects," IEEE 20th International Conference on Nanotechnology (IEEE-NANO), Montreal, Canada, 2020 🏆Awarded Best Paper

Theme 4: Machine Learning & Neuromorphic Computing Hardware

S. Kushwaha, P. R. Shamini, S. Roy, D. Spina and R. Sharma, "Machine Learning-Based Performance Optimization of Copper–Graphene Heterointerconnects," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 16, no. 3, pp. 638-641, March 2026, doi: 10.1109/TCPMT.2026.3658703.
S. A. Thomas, S. Kushwaha, R. Sharma, and D. Mrinal Das, "Design and Analysis of 3D Integrated Folded Ferro-Capacitive Crossbar Array (FC²A) for Brain-Inspired Computing System," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 14, no. 3, pp. 563-574, 2024.
S. A. Thomas, S. Kushwaha, R. Sharma, and D. M. Das, "Modeling and Comparing the Impact of Resistive and Capacitive Crossbar Associated Parasitics of Neuromorphic Circuits," 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES), Gdansk, Poland, 2024. 🏆Awarded Best Paper

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