Transistor as a buffer

NPN buffer for analog signals (single supply)

A NPN or PNP transistor in the common collector (emitter follower) configuration is generally used as a voltage buffer because of the high input impedance and low output impedance of this configuration.  The high input impedance is necessary, so the input signal is not affected significantly. The low input impedance allows driving enough current into the circuit that is connected to the output.
The amplification of a common collector configuration is slightly less than 1 and there is a voltage offset of 0.7V due to the base emitter pn junction drop.
In the figure below, the NPN version of an emitter follower is shown that can be used to buffer an analog signal:

In the figure above, the emitter follower is build around a BC547 small signal NPN transistor and is powered by a 9V DC supply. The supply voltage can be any voltage, but should be equal to or higher than the maximum input voltage. The output voltage can not be higher than the supply voltage, so the supply voltage should be chosen high enough for the buffer to handle the input voltage. The minimum input voltage should be equal to or higher than 0.7V, because the base-emitter pn junction needs at least 0.7V to make the transistor conduct. Only when the base-emitter junction of the transistor is forward biased, the transistor will draw current from the collector, that is connected to the power supply. The emitter current is more or less equal to the collector current. This is how the buffering function works: the small base current controls a much higher collector, and thus emitter, current. The emitter current can be magnitudes larger than the base current. A small current controls a much larger current, in this case directly coming from the 9V power supply.
The input impedance of this circuit ash shown above is around 450kOhm.
When we input a sinusoidal voltage with a minimum of 0.7V and a maximum of 9V, the output signal will be minimum 0V and maximum 8.3V. So the output is DC-offset 0.7V downwards towards the reference ground due to the Vbe pn junction voltage drop.
If we want a good reproduction of the analog input signal with minimum distortion (no clipping), the input signal should stay away from 0.7V and also from the power supply voltage, in this case 9V. Let's say that we get a good reproduction when the input signal is between 1V and 8V, so we have some headroom both towards the reference ground and the power supply rail.

PNP buffer for analog signals (single supply)

The same type of buffer can be built with a PNP transistor. While the output signal of an NPN buffer is DC-offset 0.7V downwards towards reference ground, the output of a PNP buffer is DC-offset 0.7V upwards towards the power supply rail due to the Vbe np junction voltage drop.
In the figure below, the PNP version of the buffer is shown:

For a good reproduction of the analog input signal with minimum distortion, the input signal needs to stay away from the supply rail voltage minus 0.7V and also from 0V. Let's say that we have a good reproduction when the input signal is between 1V and 8V, so there is enough headroom towards reference ground and the power supply rail.

Offset cancelling complementary transistor buffer for analog signals (single supply)

With the NPN as well as the PNP buffer, the output is DC-offset either downwards or upwards relative to the input signal due to the voltage drop over the Vbe junction. But there is a way to minimize this DC-offset between the input and output, namely by combining the above described NPN-buffer with the PNP buffer as shown in the figure below:

To minimize the DC-offset at the output signal, the transistors need to be matched and thermally coupled, so the emitter currents of both transistors are the same. The input impedance of the circuit as shown above is about the same as the NPN buffer, namely about 450kOhm.

Note:
Even when both transistors (Q1 and Q2) are perfectly matched, the DC-offset will be maximum 50mV. This is because the base current for Q2 is delivered via R2 causing some unbalance between both transistor sections.

Watch out for the emitter follower oscillator!

The NPN and PNP emitter follower buffers described above are prone to high frequency oscillations caused by parasitic inductance of wiring/copper traces in combination with parasitic capacitance and load capacitance.  Therefor, it is always good practice to provide a base resistor of 22 to 100 Ohms. This base resistor (base stopper) will bring down the Q-factor of the LC-resonance circuit formed by the parasitic inductance and capacitance, so high frequency oscillations can not occur anymore.

How to make a buffer for digital signals ?

What if we need a buffer for digital signals ?
In that case, the input signal will be a square wave alternating between 0 and f.e. 5V. We want the output signal to be a good reproduction of the square wave input signal, regardless of the kind of load that is connected to the output of the buffer. So, even with a capacitive load, the edges of the square wave at the output must not be delayed.
All of the above circuits are not suited to drive f.e. capacitive loads. The circuits only have 1 transistor at the output that can either sink or source relative high currents to charge or discharge the capacitance at the output fast when the transistor conducts. But when the transistor does not conduct, the output capacitance has to be charged or discharged by the resistor, which forms a low pass filter with the output capacitance. As a result, either the rising or the falling square wave edge will be delayed.
See figures below:

Push-pull buffer for digital or analog signals

In the figures above, the capacitive load at the output of the buffers is represented by the 100pF capacitor. The graphs show how the square wave edges are affected by this capacitive load. I've chosen for a 5V power supply as an example when you want to buffer 5V level digital signals.
To solve this problem, we need a buffer that has 2 transistors at the output: one that sources current to the output and one that sinks current from the output.
This is called a push-pull output stage.
In the figure below, this kind of buffer is shown:

With this kind of push-pull stage, the output capacitance can be charged and discharged very fast with the low impedance of the conducting transistor. When Q1 conducts, current is sourced directly from the power supply to charge the capacitive load. When Q2 conducts, the capacitive load is discharged by sinking current directly to ground. Because we charge and discharge the capacitor with a high current via the low impedance of a conducting transistor, the RC time-constant is very low, so the influence of the capacitance is minimal.
The input impedance of the circuit as shown above is around 480kOhm.

Note:
Note that the output goes down to 0V. This is because with a 0V input, Q1 does not conduct, so the emitter of Q2 can be seen a floating and will also be 0V.

Note:
Note that the output voltage will be 0.7V less than the input voltage. This generally is not a problem for digital signals, since their threshold values are a lot lower (f.e. TLL input levels are: < 0.8V is low and > 2V is high, and CMOS input levels are: < 1.5V is low and > 3.5V is high).

Note:
It is good practice to add a base resistor of 22 to 100 Ohms in series with the input signal going to both base terminals of Q1 and Q2. This resistor will prevent high frequency oscillations caused by the combination of parasitic inductance due to wiring/copper traces in combination with parasitic capacitance and load capacitance.

Applications of the push-pull output stage:

• This kind of push-pull stage can be used to drive the gate of a power MOSFET, that usually have a gate capacitance around 1000 pf (1 nF). When driving the gate of such a MOSFET with a digital PWM signals directly without a proper gate diver, the edges of the PWM signal would get slowed down. The MOSFET will open and close slowly instead of fast and abruptly, resulting in extra power dissipation, heating up the MOSFET considerably. See figure below for the push-pull power MOSFET gate driver:

• • The push-pull stage can also be used as a current booster for an analog OPAMP amplifier, so the OPAMP is able to drive more current into the load.
    See figure below for the OPAMP output current booster:

Dual symmetrical supply push-pull buffer for analog signals

Until now, we concentrated on single supply buffer circuits with input signals that are in between reference ground and the supply rail.
But when we want to buffer analog signals that alternate around reference ground, we will need a buffer with a symmetrical power supply.
In the following figure, such a buffer, based on the push-pull configuration, is shown:

The graphs in the figure show the input and the output signal. We have chosen a symmetrical power supply of +9V and -9V and a sinusoidal input signal swinging between +9V and -9V. The output will be between +8.3V and -8.3V because of the Vbe voltage drops (= 0.7V) of respectively Q1 and Q2. Q1 conducts when the input signal exceeds +0.7V, so the base emitter junction of Q1 is forward biased. Q2 conducts when the input signal goes below -0.7V, so the base emitter junction of Q2 is forward biased. Both Q1 and Q2 are not conducting when the input signal voltage is in between +0.7V and -0.7V. So the circuit has a dead-zone in which both transistors are not conducting. This can be seen in the Vout graph, where the output signal is distorted when the input signal crosses the 0V level. This cross-over distortion is exaggerated a bit in the graph to make things more clear.
This way, the buffer is not really suited for analog signals when we want the output signal to be a proper reproduction of the input signal.

Cross-over distortion cancellation method

To minimize the cross-over distortion problem, we need to somehow eliminate the dead-zone to prevent cross-over distortion.  One trick to do this is using diodes, as shown in the figure below:

The 2 circuits above behave identical. In the left circuit, silicon diodes D1 and D2 are used to eliminate the dead-zone and thus the distortion at the output. In the right circuit, so called "diode-connected-transistors" Q3 and Q4 are connected as diodes and have the same effect as using normal diodes. When Q3, Q4, Q5, Q6 are matched transistors and are coupled thermally (like being on a same chip), they will have exactly the same Vbe drops and the dead-zone will be cancelled out perfectly.
How the dead-zone is cancelled out ? D1 and D2 are forward biased by R1 and R2, so both diodes will have a 0.7V voltage drop. Let's assume that the input voltage is slightly above 0V, f.e. at 0.1V. The base voltage of Q1 would then be the input voltage level, being 0.1V plus the voltage drop over D1, which is 0.7V. So the voltage at the base of Q1 would be 0.8V when the input signal is 0.1V. This means that Q1 will be conducting already at this 0.1V. Without D1, Q1 would only conduct when the input signal would rise above 0.7V.
The same applies to Q2. When the input signal would be -0.1V, the voltage at the base of Q2 would be -0.1V - 0.7V (voltage drop of D2) = -0.8V. So Q2 will conduct when the input signal is slightly below -0.1V.  Without D2, Q2 would only conduct when the input signal would fall below -0.7V.
This way we cancel out the dead-zone and thus the cross-over distortion that would appear without D1 and D2 (left circuit) or Q3 and Q4 (right circuit).

The input impedance of the circuit as shown above is about 5kOhm, which is the parallel resistance of R1 // R3. When R1 and R2 would both have been 47k, then the input impedance of the circuit would be around 23kOhm. But then the distortion would increase because the voltage drop over D1 and D2 would be lower due to the lower bias current.

Note:
Note that the input signal amplitude can not be the same as the supply voltage, but needs to be f.e. 1V lower than the supply voltage. This is because the input signal must be able to lift the voltage at the base of Q1 up to the positive power supply voltage. And also to lower the voltage at the base of Q2 down to the negative power supply. When the input signal would alternate between +9V and -9V, the output would be distorted.

Note:
Note that the input impedance of the circuits with the diodes is a significantly lower than the circuit without the diodes. This is because the input signal has to fight the bias current to lift the voltage at the base of Q1 or lower the voltage at the base of Q2. The bias current flows through the diodes via R1 and R2. A high input impedance is required for a good buffer, so this is not a good solution and requires a third transistor or an OPAMP to drive current into the circuit.
See the circuit below where an OPAMP is used to drive the push-pull output stage:

Dual symmetrical supply "diamond" buffer

The disadvantage of the previous circuit with the diodes was the low input impedance, requiring an OPAMP or a third transistor to drive the push-pull output stage.  A better circuit is shown below.  This is a complementary emitter follower configuration where the 2 outputs are combined using electrolytic capacitors. The capacitors only pass the AC signal and block the DC content of the signal. So the 0.7V negative or positive offset caused by the emitter followers is cancelled out, and the output nicely swings around zero.
The value of the output capacitors together with the load R2 form an RC high pass filter.  So the value of the capacitors together with the value of the load resistance determine the lowest frequency that will be passed to the output.

Connecting the emitters directly to the load without the capacitors would turn the circuit into a push-pull output. If you don't see it, check the circuits below where I moved the transistors around so you see the push-pull output appearing.
Without the capacitors, we would have the cross-over distortion that is typical for the push-pull output stage.

A better circuit that does not need the output capacitors, has a high input impedance and no cross-over distortion is the "diamond buffer", which is shown in the circuit below:

The circuit can be seen as a combination of 2x complementary transistor buffers put on top of each other.
When the input signal is 0V, Q2 and Q3 will both be conducting and drawing current through R1 and R5 respectively. The emitter of Q2 will be 0.7V higher than the input signal at the base of Q2 (being 0V), thus +0.7V. The emitter of Q3 will be 0.7V lower than the input signal at the base of Q3 (being 0V), thus -0.7V. When the emitter of Q2 is at +0.7V, the base of Q1 is also at +0.7V, so this transistor will be slightly conducting. The emitter of Q1 will be 0.7V lower than the base, so 0V. The same goes for the emitter of Q4, which will also be at 0V. So with an input signal of 0V all the transistors will be conducting, meaning that there will be no cross-over distortion or dead-zone, where both output transistors do not conduct. Only when the input signal goes up to the positive or negative power supply rail, one of the output transistors will be cut off, causing distortion due to clipping. Therefor, the input signal should be about 1V less than the power supply voltage, so there is enough headroom for the transistors to operate in without clipping.
The input impedance of the circuit shown is about 230kOhm. R1 and R5 determine the input impedance. The higher R1 and R5, the higher the input impedance, but also the bigger the distortion, because these resistors also determine the base current for the push-pull output stage transistors Q1 and Q4. When this base current becomes too low, the output transistor can not deliver enough current to drive the load.
More elaborate versions of the diamond buffer configuration can be found as a sub-circuit in discrete amplifiers and in OPAMPs, where R1 and R5 mostly are replaced by constant current sources or current mirrors. 

Dual symmetrical supply differential amplifier based buffer for analog signals

Another type of buffer is using what can be seen as an extremely basic discrete OPAMP that is build up with 3 transistors. 
In the figure below, this discrete OPAMP is shown:

In fact, the circuit is a differential amplifier formed by of Q2 and Q3 (long-tailed pair).  At the collector of Q2 we find an inverted version of the input signal. This inverted input signal is again inverted by Q1, so at the collector of Q1 we find a non-inverted version of the input signal, which is the output of the discrete OPAMP.
To configure the OPAMP as a voltage follower/buffer, we need to connect the output to the inverting input so we get 100% negative feedback, causing the output to follow the voltage on the non-inverting input. In the figure below, the buffer configuration is shown:

The input impedance of the buffer as shown is about 420kOhm, mainly determined by R3.
C1 limits the bandwidth of the buffer to about 1MHz and prevents high frequency oscillations.
The input signal should allow enough headroom towards the positive and negative power supply rails, so the output signal does not get distorted by clipping.