PIN diode attenuator simulation

Created: Nov. 2022

This design was previously published without circuit simulation [1-2]. This post shows how the attenuator can be simulated and compares simulated vs. measured results.

Although the constant impedance PI attenuator can be replicated with just 3 diodes, the resultant circuit is assymmetrical and requires a rather complicated bias network. The 4-diode attenuator was devised to overcome these deficiency [3]. As a bonus, it also produces less distortion.

The attenuator requires a constant voltage, V+, and a variable control voltage, Vc. With V+ equal to 1.25 V, the variable control voltage will range from 0 V to about 5 V.

Fig. 1 shows a schematic diagram of the pi-attenuator circuit

The attenuator was implemented on an FR-4 printed-circuit board (PCB) of 0.8 mm thickness. However, this low cost material curtails the attenuator's high frequency performances by increasing loss.

Fig. 2 Photo of assembled attenuator showing its compact form & low component count

Fig. 3 shows the PCB layout & component placement

Table 1 Bill of material

The HSMP-3816 is a diode quad housed in a five-pin, leadfree SOT-25 surfacemount package. The pi-connected quad PIN diodes are adjacent die selected from the same wafer for closely matched electrical characteristics. In addition to the obvious size advantage, bundling four well-matched PIN diodes into one SOT-25 package helps ensure better symmetry between the attenuator's input and output arms than is realizable using physically distinct parts.

Fig. 4 Internal view of HSMP-3816 PIN diode array in SOT-25 package

PIN diodes cannot be modeled on SPICE because the standard PN diode model has no provision for provision for minority carrier lifetime; i.e. this parameter permits the PIN diode to behave like a fixed resistor at RF.

A workaround is to model the PIN diode using a linear equation [4] as per implemented in the APLAC simulator. The HSMP-381x's model parameters were obtained here [5].

The equivalent circuit model has a three-level hierarchy: APLAC linear model of diode, packaged diode array and complete attenuator. For convenience, the RF connectors are not modeled.

Fig. 5 Equivalent circuit models of (top to bottom) diode chip, package diode array, complete attenuator and how the three levels relate

Results

The simulated attenuation vs. frequency shows good agreement with measurement over 10-1000 MHz (fig. 6a). The discrepancy between simulation & measurement is likely due to errors in the models for the diode array, PCB and other components.

The minimum attenuation is ~5 dB corresponding to Vc = 5V. Maximum attenuation is achieved at Vc = 0.5V. The frequency responses at 1.5V and 5.0V are flat over 10-1000 GHz. However, at 0.5V, the attenuation reduces with higher frequencies. This deleterious characteristic is caused by the parasitic capacitance in the series PIN diodes.

Fig. 6a Simulated & measured attenuation agree almost perfectly at 1.5V (red trace) and 5.0V (green trace). There is more error at 0.5V, but the general trend is correctly predicted

In applications requiring a flat response, deliberately limiting the maximum attenuation to 45 dB (Vc = 1.0V) allows operation up to ~200 MHz (fig. 6b).

Fig. 6b: The same data in the previous graph shown over a reduced frequency span.

Most of the control range is concentrated between 0.7 to 3.0V. Above 3.0V, the attenuation only reduces slightly (fig. 7).

Fig. 7 Simulated & measured attenuation at 100 MHz as a function of control voltage Vc. Almost perfect agreement

At maximum attenuation (Vc = 0V), the return loss (RL) is very good over a wide frequency range (fig. 8). Due to model inaccuracies, the simulated RL is significantly worse than measurement.

Fig. 8 Simulated & measured return loss at 0V. Error <=15 dB. However, the error is not worrying because the return loss is very good

Likewise at minimum attenuation (Vc = 5V), the return loss (RL) is very good over a wide frequency range (fig. 9). Again, the simulated RL is poorer than experimental.

Fig. 9 Simulated & measured return loss at 5V. Error <=3 dB

Conclusion

PIN diode attenuators can be simulated with reasonable accuracy using the APLAC equation based model

References

[1] Application note 5262, "HSMP-3816 High Linearity PIN Diode Pi Attenuator Using a Diode Quad in Low Cost SOT-25 Package", Avago, Jun. 2006.

[2] C. L. Lim, S.C. Goh & Y.C. Lim, "Diode quad is foundation for PIN diode attenuator," Microwaves & RF, May 2006. Available: http://mwrf.com/semiconductor/diode-quad-foundation-pin-diode-attenuator

[3] "Waugh attenuator", May 2011. Available: https://www.microwaves101.com/encyclopedias/waugh-attenuator

[4] Joe Walston, “SPICE Circuit Yields Recipe for PIN Diode”, Microwaves and RF, pp. 78-89, Nov., 1992.

[5] "SPICE Library: PIN Diode Models", Available: http://www.hp.woodshot.com/hprfhelp/design/SPICE/pins.htm

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