Publications

Google Scholar profile

Books & Book Chapters

  1. Phase Change Memory: From Devices to Systems                                                                                                                                                          Moinuddin K. Qureshi, Sudhanva Gurumurthi and Bipin Rajendran, Synthesis Lectures, Morgan Claypool, 2011.
  2. Architecture in Advances in Neuromorphic Hardware Exploiting Emerging Nanoscale Devices,                                                                U. Ganguly & B. Rajendran, Novel Biomimetic Si Devices for Neuromorphic Computing, Edited by M. Suri, Published by Springer, 2017.

Journal Papers

  1. Nandakumar S R, Marie Minvielle, Saurabh Nagar, Catherine Dubourdieu, Bipin Rajendran, A 250 mV Cu/SiO2/W memristor with half-integer quantum conductance states, Nano Letters, 2016, 16 (3), pp 1602–1608.
  2. B. Rajendran & F. Alibart, Neuromorphic Computing Based on Emerging Memory Technologies, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2016.
  3. J. Bhal, B. Rajendran & B. Muralidharan, Programming current reduction via enhanced asymmetry-induced thermoelectric eff.ects in vertical nanopillar phase change memory cells, IEEE Transactions on Electron Devices, 62 (12), 4015-4021, 2015.
  4. S. Mandal, A. El-Amin, K. Alexander, B. Rajendran & Rashmi Jha, Novel synaptic memory device for neuromorphic computing, Nature Scientific Reports, 4, 5333; DOI:10.1038/srep05333 (2014).
  5. R. Mandapati, A. Borkar, V. S. S. Srinivasan, P. Bafna, P. Karkare, S. Lodha, B. Rajendran, and U. Ganguly, On Pairing of Bipolar RRAM Memory with NPN Selector based on Set/Reset Array Power Considerations. IEEE Transactions on Nanotechnology, Volume:12 ,  Issue: 6, Nov. 2013 .
  6. B. L. Jackson$, B. Rajendran$, G. S. Corrado$, M. Breitwisch, G. W. Burr, R. Cheek, K. Gopalakrishnan, S. Raoux, C. T. Rettner, A. Padilla, A. G. Schrott, R. S. Shenoy, B. N. Kurdi, C. H. Lam, & D. S. Modha. Nano-Scale Electronic Synapses using Phase Change Devices. ACM Journal on Emerging Technologies, 9, 2, Article 12, May 2013. ($These authors contributed equally to this work).
  7. B. Rajendran, Y. Liu, J. Seo, K. Gopalakrishnan, L. Chang, D. Friedman and M. Ritter. Specifications of Nanoscale Devices & Circuits for Neuromorphic Computational Systems. IEEE Transactions on Electron Devices, Volume: 60, Issue: 1, Jan. 2013.         
  8. N. Wang, E. J. O'Sullivan, P. Herget, B. Rajendran, L. Krupp, L. T. Romankiw, B. C. Webb, R. Fontana, E. Duch, E. Joseph, S. Brown, X. Hu, G. Decad, N. Sturcken, K. L. Shepard & W. J. Gallagher. Integrated on-chip inductors with electroplated magnetic yokes. Journal of Applied Physics, 111, 07E732 (2012).(Invited).
  9. L. Li, K. Lu, B. Rajendran, T. D. Happ, H-L. Lung, C. Lam & M Chan. Driving Device Comparison for Phase Change Memory. IEEE Transactions on Electron Devices, Vol. 58, No. 3, pages 664-671, 2011.
  10. H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. Reifenberg, B. Rajendran, M. Asheghi & K. Goodson. Phase Change Memory. Proceedings of the IEEE, Vol. 98, No. 12, December 2010.(Invited).
  11. G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. A. Lastras, A. Padilla, B. Rajendran & S. Raoux. Phase Change Memory Technology. Journal of Vacuum Science & Technology B, Vol. 28, Issue 2, pp. 223-262, 2010.(Invited)
  12. B. Rajendran, M. Breitwisch, M-H. Lee, G. W. Burr, Y-H. Shih, R. Cheek, A. Schrott, C-F. Chen, E. Joseph, R. Dasaka, H-L. Lung & C. Lam. Dynamic Resistance - A Metric for Variability Characterization of Phase Change Memory. IEEE Electron Device Letters, Vol 30, Issue 2, pages 126-129, 2009.
  13. B. Rajendran, R. Shenoy, D. Wittie, N. Chokshi, R. DeLeon, G. Tompa & R. F. W. Pease. Low Thermal Budget Processing for Sequential 3D IC Fabrication. IEEE Transactions on Electron Devices, Vol. 54, No. 4, Pages 707-713, April 2007.
  14. F. Crnogorac, D. J. Witte, Q. Xia, B. Rajendran, D. S. Pickard, Z. Liu, A. Mehta, S. Sharma, A Yasseri, T. Kamins, S. Y. Chou & R. F. W. Pease. Nano-Graphoepitaxy of Semiconductors for 3D Integration. Journal of Microelectronic Engineering, Volume 84, Pages 891-894, May-August 2007.
  15. D. Witte, F. Crnogorac, D. Pickard, A. Mehta, Z. Liu, B. Rajendran, P. Pianetta & R. F. W. Pease. Lamellar Crystallization of Silicon for 3-dimensional Integration. Journal of Microelectronic Engineering, Volume 84, Pages 1186-1189, May-August 2007.
  16. Z. Li, B. Rajendran, T. I. Kamins, X. Li, Y. Chen & R. S. Williams. Silicon Nanowires for Sequence-Speci.c DNA Sensing: Device Fabrication and Simulation. Applied Physics, A 80, 1257-1263, 2005.  

Conference Papers

  1. P. Tandon, Y. Malviya and B. Rajendran, E.fficient and Robust Spiking Neural Circuit for Navigation Inspired by Echolocating Bats, Thirtieth Annual Conference on Neural Information Processing Systems, 2016.
  2. Nandakumar S. R. and Bipin Rajendran, Verilog-A Compact Model for a Novel Cu/SiO2/W Quantum Memristor., International Conference on Simulation of Semiconductor Processes and Devices2016.
  3. Nandakumar S. R. and Bipin Rajendran, Physics-based Switching Model for Cu/SiO2/W Quantum Memristor., Device Research Conference, 2016.
  4. A. Goyal, M. Autade, G. D. Singh, P. Desai, B. Rajendran & M. Jain. Analytics For a Controlled Experiment to Determine Optimal Thermal Insulation for Building Envelopes. Building Simulation Conference 2015.
  5. J. Demme, S. Nowick, B. Rajendran & S. Sethumadhavan. Increasing Reconfigurability with Memristive Interconnects. 33rd IEEE International Conference on Computer Design, 2015.
  6. S. Kulkarni & B. Rajendran. Scalable Digital CMOS Architecture for Spike based Supervised Learning. 16th International Conference on Engineering Applications of Neural Networks, 2015.
  7. V. Ostwal, B. Rajendran & U. Ganguly. A Circuit Model for a Si-based Biomimetic Synaptic Time-keeping Device. International Conference on Simulation of Semiconductor Processes and Devices, 2015.
  8. N. Anwani & B. Rajendran. Normalized Approximate Descent based Supervised Learning Rule for Spiking Neurons. International Joint Conference on Neural Networks, 2015.
  9. S. Santurkar & B. Rajendran. C. elegans chemotaxis inspired neuromorphic circuit for contour tracking and obstacle avoidance. International Joint Conference on Neural Networks, 2015.
  10. S. Thorat & B. Rajendran. Arithmetic Computing via Rate Coding in Neural Circuits with Spike-triggered Adaptive Synapses. International Joint Conference on Neural Networks, 2015.
  11. C. P. Narisetty, K. Saboo & B. Rajendran. Composer Classification based on Temporal Coding in Adaptive Spiking Neural Networks. International Joint Conference on Neural Networks, 2015.
  12. V. Ostwal, R. Meshram, B. Rajendran & U. Ganguly. An ultra-compact and low power neuron based on SOI platform. International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2015.
  13. C. Shetty, P. Shah, S. Nitchith, R. Rawat, Nandakumar S. R, S. Kulkarni & B. Rajendran. Live Demonstration: Spiking Neural Circuit Based Navigation Inspired by C. elegans Thermotaxis. IEEE International Symposium on Circuits & Systems 2015.
  14. P. J. Nair, C. Chou, B. Rajendran & M. K. Qureshi. Reducing Read Latency of Phase Change Memory via Early Read and Turbo Read. IEEE International Symposium on High Performance Computer Architecture, 2015.
  15. A. Kothiyal, B. Rajendran & S. Murthy. Delayed Guidance: A teaching-learning strategy to develop ill-structured problem solving skills in engineering. IEEE International Conference on Learning and Teaching in Computing and Engineering, 2015.
  16. A. Anand, A. Kothiyal, B. Rajendran & S. Murthy. Guided Problem Solving and Group Programming - A Technology-Enhanced Teaching-Learning Strategy for Engineering Problem Solving. IEEE International Conference on Technology for Education, 2014.
  17. N. Panwar, D. Kumar, N. K. Upadhyay, P. Arya, U. Ganguly and B. Rajendran - Memristive Synaptic Plasticity in PCMO RRAM by Bio-mimetic Programming, Device Research Conference, 2014.
  18. R. Meshram,  B. Rajendran and U. Ganguly - Biomimetic 4F2 synapse with intrinsic timescale for pulse based STDP by I-NPN selection deviceDevice Research Conference, 2014.
  19. A. Bora, A. Rao and  B. Rajendran.  Mimicking the worm - an adaptive spiking neural circuit for contour tracking inspired by  C. Elegans  thermotaxisInternational Joint Conference on Neural Networks, 2014.
  20. A. Singha, B. Muralidharan and  B. Rajendran. Analog Memristive Time Dependent Learning Using Discrete Nanoscale RRAM Devices. International Joint Conference on Neural Networks, 2014.
  21. B. Rajendran, A. K. Henning, B. Cronquist and Z. Or-Bach. Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D ICsThe IEEE International Conference on 3D System Integration, 2013.
  22. A. K. Henning, B. Rajendran, B. Cronquist and Z. Or-Bach. Thermal Considerations for Monolithic Integration of Three-Dimensional Integrated Circuits, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2013.
  23. S. Deshmukh, S. Lashkare, B. Rajendran, U. Ganguly. I-NPN: A sub-60mV/decade, sub-0.6V selection diode for STTRAM, Device Research Conference, 2013.
  24. B. Rajendran, Y. Liu, J. Seo, K. Gopalakrishnan, L. Chang, D. Friedman and M. Ritter. RRAM Devices for Large Neuromorphic Systems. Non-Volatile Memories Workshop, 2013.
  25. M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian & V. Srinivasan. Efficient Scrub Mechanisms for Error-Prone Emerging Memories. IEEE International Symposium on High Performance Computer Architecture, 2012.
  26. S Yarlanki, B Rajendran, H Hamann. Estimation of turbulence closure coefficients for data centers using machine learning algorithms.  13th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012. 
  27. B. Rajendran, Phase Change Memory Devices for Cognitive Computing, CMOS Emerging Technologies Research Conference, 2012.
  28. J. Seo, B. Brezzo, Y. Liu, B. D. Parker, S. K. Esser, R. K. Montoye, B. Rajendran, J. A. Tierno, L. Chang, D. S. Modha & D. J. Friedman. A 45nm CMOS Neuromorphic Chip with a Scalable Architecture for Learning in Networks of Spiking Neurons. IEEE Custom Integrated Circuits Conference, 2011.
  29. B. Rajendran, R. Cheek, L. Lastras, M. Franceschini, M. Breitwisch, A. Schrott, J. Li, R. Montoye, L. Chang & C. Lam. Demonstration of CAM and TCAM using Phase Change Devices. IEEE International Memory Workshop, 2011.
  30. M. Awasthi, M. Shevgoor, K. Sudan, R. Balasubramonian, B. Rajendran & V. Srinivasan. Handling PCM Resistance Drift with Device, Circuit, Architecture and System Solutions. Second Annual Non-Volatile Memories Workshop, 2011.
  31. L. A. Lastras-Montano, M. M. Franceschini, B. Rajendran & C. Lam. Coding for sensing in content addressable memories. IEEE International Symposium on Information Theory, 2010. 
  32. Y. H. Shih, M. H. Lee, M. Breitwisch, R. Cheek, J. Y. Wu, B. Rajendran, Y. Zhu, E. K. Lai, C. F. Chen, H. Y. Cheng, A. Schrott, E. Joseph, R. Dasaka, S. Raoux, H. L. Lung & C. Lam. Understanding Amorphous States of Phase-Change Memory Using Frenkel-Poole Model. International Electron Devices Meeting 2009.
  33. B. Rajendran, M. Breitwisch, R. Cheek, M-H. Lee,Y-H. Shih, H-L. Lung & C. Lam. Characterization of Poly-silicon Emitter BJTs as Access Devices for Phase Change Memory. IEEE International Symposium on VLSI Technology, Systems, and Applications, 2009.
  34. C.-F. Chen, A. Schrott, M. H. Lee, S. Raoux, Y. H. Shih, M. Breitwisch, F. H. Baumann, E. K. Lai, T. M. Shaw, P. Flaitz, R. Cheek, E. A. Joseph, S. H. Chen, B. Rajendran, H. L. Lung & C. Lam. Endurance Improvement of Ge2Sb2Te5 based Phase Change Memory. IEEE International Memory Workshop, 2009.
  35. K. Lu, B. Rajendran, T. D. Happ, R. M. Y. Ng, H-L. Lung, C. Lam & M. Chan. Optimized Scaling of Diode Array Design for 32nm Node Phase Change Memory. IEEE International Symposium on VLSI Technology, Systems, and Applications, 2008.
  36. B. Rajendran, J. Karidis, M-H. Lee, M. Breitwisch, G. W. Burr, Y-H. Shih, R. Cheek, A. Schrott, H-L. Lung & C. Lam. Analytical Model for RESET Operation of Phase Change Memory. International Electron Devices Meeting 2008.
  37. B Rajendran, MH Lee, M Breitwisch, GW Burr, YH Shih, R Cheek, A Schrott, CF Chen, M Lamorey, E Joseph, Y Zhu, R Dasaka, PL Flaitz, FH Baumann, HL Lung, C Lam, On the dynamic resistance and reliability of phase change memory, Symposium on VLSI Technology, 2008 
  38. Y. H. Shih, J. Y. Wu, B. Rajendran, M. H. Lee, R. Cheek, M. Lamorey, M. Breitwisch, Y. Zhu, E. K. Lai, C.F. Chen, E. Stinzianni , A. Schrott, E. Joseph, R. Dasaka, S. Raoux, H. L. Lung & C. Lam. Mechanisms of Retention Loss in Ge2Sb2Te5-based Phase-Change Memory. International Electron Devices Meeting 2008.
  39. M. Chan, K. Lu, T. D. Happ, B. Rajendran, H-L. Lung & C. Lam. Modeling of PN Diode Based Phase-Change Memory Access Circuit. Workshop on Compact Modeling 2008.
  40. T. Nirschl, J. B. Philipp, T. D. Happ, G. W. Burr, B. Rajendran, M. H. Lee, A. Schrott, M. Yang, M. Breitwisch, C. F. Chen, E. Joseph, M. Lamorey, R. Cheek, S.H. Chen, S. Zaidi, S. Raoux, Y. C. Chen, Y. Zhu, R. Bergmann, H. L. Lung & C. Lam. Write Strategies for 2 and 4-bit multi level Phase Change Memory. International Electron Devices Meeting 2007.
  41. M. Breitwisch, T. Nirschl, C.F. Chen, Y. Zhu, M. H. Lee, M. Lamorey, G. W. Burr, E. Joseph, A. Schrott, J. B. Philipp, R. Cheek, T. D. Happ, S. H. Chen, S. Zaidi, P. Flaitz, J. Bruley, R. Dasaka, B. Rajendran, S. Rossnagel, M. Yang, Y. C. Chen, R. Bergmann, H. L. Lung & C. Lam. Novel Lithography-Independent Pore Phase Change Memory. VLSI Technology Symposium 2007.
  42. T. I. Kamins, S. Sharma, M. S. Alam, B. Rajendran & R. S. Williams. Metal catalyzed, self-assembled, bridging nanowires and their potential use as sensors. International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures, 2005.
  43. B. Rajendran, P. Kapur, K. C. Saraswat & R. F. W. Pease. Power/ Performance/ Reliability Analysis for Copper Interconnects. ACM International Workshop on System Level Interconnect Prediction 2004.
  44. B. Rajendran, S. Jain, T. A. Kramer & R. F. W. Pease. Thermal Simulation of Laser Annealing for 3D Integration. VLSI Multi-level Interconnect Conference 2003.
  45. B. Rajendran, V. Kheterpal, A. Das, J. Majumder, C. Mandal & P. P. Chakraborty. Timing Analysis of Tree-like RLC Circuits. IEEE International Symposium on Circuits and Systems 2002.
  46.  B. Rajendran, G. S. Kar, S. Sen & S. K Ray. Modeling of SiGe/Si Heterostructure pMOSFET Devices using Neural Networks. International Conference on Computers, Communication and Devices 2000.