Publications

Google Scholar profile

Books & Book Chapters

  1. Phase Change Memory: From Devices to Systems, Moinuddin K. Qureshi, Sudhanva Gurumurthi and Bipin Rajendran, Synthesis Lectures, Morgan Claypool, 2011.
  2. Advances in Neuromorphic Hardware Exploiting Emerging Nanoscale Devices, U. Ganguly & B. Rajendran, Novel Biomimetic Si Devices for Neuromorphic Computing, Edited by M. Suri, Published by Springer, 2017.

Journal Papers

  1. Irem Boybat, Manuel Le Gallo, S. R. Nandakumar, Timoleon Moraitis, Tomas Tuma, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, and Evangelos Eleftheriou, Neuromorphic computing with multi-memristive synapses, Nature Communications, 9, Article number: 2514 (2018).
  2. S. R. Kulkarni & B. Rajendran, Spiking Neural Networks for Handwritten Digit Recognition - Supervised Learning and Network Optimization, Elsevier Neural Networks. Volume 103, July 2018, Pages 118-127.
  3. N. Panwar, B. Rajendran and U. Ganguly, Arbitrary Spike-Time-Dependent Plasticity (STDP) in Memristor by Analog Waveform Engineering, IEEE Electron Device Letters, Volume: 38, Issue: 6, pp. 740-743, June 2017.
  4. Nandakumar S R, Marie Minvielle, Saurabh Nagar, Catherine Dubourdieu, Bipin Rajendran, A 250 mV Cu/SiO2/W memristor with half-integer quantum conductance states, Nano Letters, 2016, 16 (3), pp 1602–1608.
  5. B. Rajendran & F. Alibart, Neuromorphic Computing Based on Emerging Memory Technologies, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2016.
  6. J. Bhal, B. Rajendran & B. Muralidharan, Programming current reduction via enhanced asymmetry-induced thermoelectric eff.ects in vertical nanopillar phase change memory cells, IEEE Transactions on Electron Devices, 62 (12), 4015-4021, 2015.
  7. S. Mandal, A. El-Amin, K. Alexander, B. Rajendran & Rashmi Jha, Novel synaptic memory device for neuromorphic computing, Nature Scientific Reports, 4, 5333; DOI:10.1038/srep05333 (2014).
  8. R. Mandapati, A. Borkar, V. S. S. Srinivasan, P. Bafna, P. Karkare, S. Lodha, B. Rajendran, and U. Ganguly, On Pairing of Bipolar RRAM Memory with NPN Selector based on Set/Reset Array Power Considerations. IEEE Transactions on Nanotechnology, Volume:12 , Issue: 6, Nov. 2013 .
  9. B. L. Jackson$, B. Rajendran$, G. S. Corrado$, M. Breitwisch, G. W. Burr, R. Cheek, K. Gopalakrishnan, S. Raoux, C. T. Rettner, A. Padilla, A. G. Schrott, R. S. Shenoy, B. N. Kurdi, C. H. Lam, & D. S. Modha. Nano-Scale Electronic Synapses using Phase Change Devices. ACM Journal on Emerging Technologies, 9, 2, Article 12, May 2013. ($These authors contributed equally to this work).
  10. B. Rajendran, Y. Liu, J. Seo, K. Gopalakrishnan, L. Chang, D. Friedman and M. Ritter. Specifications of Nanoscale Devices & Circuits for Neuromorphic Computational Systems. IEEE Transactions on Electron Devices, Volume: 60, Issue: 1, Jan. 2013.
  11. N. Wang, E. J. O'Sullivan, P. Herget, B. Rajendran, L. Krupp, L. T. Romankiw, B. C. Webb, R. Fontana, E. Duch, E. Joseph, S. Brown, X. Hu, G. Decad, N. Sturcken, K. L. Shepard & W. J. Gallagher. Integrated on-chip inductors with electroplated magnetic yokes. Journal of Applied Physics, 111, 07E732 (2012).(Invited).
  12. L. Li, K. Lu, B. Rajendran, T. D. Happ, H-L. Lung, C. Lam & M Chan. Driving Device Comparison for Phase Change Memory. IEEE Transactions on Electron Devices, Vol. 58, No. 3, pages 664-671, 2011.
  13. H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. Reifenberg, B. Rajendran, M. Asheghi & K. Goodson. Phase Change Memory. Proceedings of the IEEE, Vol. 98, No. 12, December 2010.(Invited).
  14. G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. A. Lastras, A. Padilla, B. Rajendran & S. Raoux. Phase Change Memory Technology. Journal of Vacuum Science & Technology B, Vol. 28, Issue 2, pp. 223-262, 2010.(Invited)
  15. B. Rajendran, M. Breitwisch, M-H. Lee, G. W. Burr, Y-H. Shih, R. Cheek, A. Schrott, C-F. Chen, E. Joseph, R. Dasaka, H-L. Lung & C. Lam. Dynamic Resistance - A Metric for Variability Characterization of Phase Change Memory. IEEE Electron Device Letters, Vol 30, Issue 2, pages 126-129, 2009.
  16. B. Rajendran, R. Shenoy, D. Wittie, N. Chokshi, R. DeLeon, G. Tompa & R. F. W. Pease. Low Thermal Budget Processing for Sequential 3D IC Fabrication. IEEE Transactions on Electron Devices, Vol. 54, No. 4, Pages 707-713, April 2007.
  17. F. Crnogorac, D. J. Witte, Q. Xia, B. Rajendran, D. S. Pickard, Z. Liu, A. Mehta, S. Sharma, A Yasseri, T. Kamins, S. Y. Chou & R. F. W. Pease. Nano-Graphoepitaxy of Semiconductors for 3D Integration. Journal of Microelectronic Engineering, Volume 84, Pages 891-894, May-August 2007.
  18. D. Witte, F. Crnogorac, D. Pickard, A. Mehta, Z. Liu, B. Rajendran, P. Pianetta & R. F. W. Pease. Lamellar Crystallization of Silicon for 3-dimensional Integration. Journal of Microelectronic Engineering, Volume 84, Pages 1186-1189, May-August 2007.
  19. Z. Li, B. Rajendran, T. I. Kamins, X. Li, Y. Chen & R. S. Williams. Silicon Nanowires for Sequence-Speci.c DNA Sensing: Device Fabrication and Simulation. Applied Physics, A 80, 1257-1263, 2005.

Peer-Reviewed Conference Papers

  1. Alireza Bagheri, Osvaldo Simeone and Bipin Rajendran, Adversarial Training for Probabilistic Spiking Neural Networks, 19th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2018.
  2. Shruti R. Kulkarni, John M. Alexaides, Bipin Rajendran, Live Demonstration: Image Classification Using Bio-inspired Spiking Neural Networks, IEEE International Symposium on Circuits and Systems 2018.
  3. S. R. Nandakumar, Manuel Le Gallo, Irem Boybat, Bipin Rajendran, Abu Sebastian, and Evangelos Eleftheriou, Mixed-precision architecture based on computational memory for training deep neural networks, IEEE International Symposium on Circuits and Systems 2018.
  4. Alireza Bagheri, Osvaldo Simeone and Bipin Rajendran, Training Probabilistic Spiking Neural Networks With First-to-Spike Decoding, 42th International Conference on Acoustics, Speech, and Signal Processing, 2018.
  5. Anakha V. Babu and Bipin Rajendran, Stochastic Deep Learning in Memristive Networks, IEEE International Conference on Electronics, Circuits and Systems, 2017.
  6. Shruti R. Kulkarni, John M. Alexaides, Bipin Rajendran, Learning and Real-time Classification of Hand-written Digits With Spiking Neural Networks, IEEE International Conference on Electronics, Circuits and Systems, 2017.
  7. Shruti Kulkarni, Anakha V Babu, Bipin Rajendran, Spiking Neural Networks - Algorithms, Hardware Implementations, and Applications, IEEE 60th International Midwest Symposium on Circuits and Systems, 2017. Invited.
  8. S. R. Nandakumar, Bipin Rajendran, Synaptic Plasticity in a Memristive Device below 500mV, The 231st Meeting of the Electrochemical Society, 2017. Invited.
  9. Irem Boybat, Manuel Le Gallo, S. R. Nandakumar, Timoleon Moraitis, Tomas Tuma, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, and Evangelos Eleftheriou, An efficient synaptic architecture for artificial neural networks, 17th Non-Volatile Memory Technology Symposium 2017. Awarded 3rd prize in best poster category.
  10. S. R. Nandakumar, I. Boybat, M. Le Gallo, A. Sebastian, B. Rajendran, and E. Eleftheriou, Supervised Learning in Spiking Neural Networks with MLC PCM Synapses, Device Research Conference, 2017.
  11. P. Tandon, Y. Malviya and B. Rajendran, Efficient and Robust Spiking Neural Circuit for Navigation Inspired by Echolocating Bats, Thirtieth Annual Conference on Neural Information Processing Systems, 2016.
  12. Nandakumar S. R. and B. Rajendran, Verilog-A compact model for a novel Cu/SiO2/W quantum memristor, International Conference on Simulation of Semiconductor Processes and Devices, 2016.
  13. Nandakumar S. R. and B. Rajendran, Physics-based Switching Model for Cu/SiO2/W quantum memristor, Device Research Conference, 2016.
  14. A. Goyal, M. Autade, G. D. Singh, P. Desai, B. Rajendran & M. Jain, Analytics For a Controlled Experiment to Determine Optimal Thermal Insulation for Building Envelopes, Building Simulation Conference 2015.
  15. J. Demme, S. Nowick, B. Rajendran & S. Sethumadhavan, Increasing Reconfigurability with Memristive Interconnects, 33rd IEEE International Conference on Computer Design, 2015.
  16. S. Kulkarni & B. Rajendran, Scalable Digital CMOS Architecture for Spike based Supervised Learning, 16th International Conference on Engineering Applications of Neural Networks, 2015.
  17. V. Ostwal, B. Rajendran & U. Ganguly, A Circuit Model for a Si-based Biomimetic Synaptic Time-keeping Device, International Conference on Simulation of Semiconductor Processes and Devices, 2015.
  18. N. Anwani & B. Rajendran, Normalized Approximate Descent based Supervised Learning Rule for Spiking Neurons, International Joint Conference on Neural Networks, 2015.
  19. S. Santurkar & B. Rajendran, C. elegans chemotaxis inspired neuromorphic circuit for contour tracking and obstacle avoidance, International Joint Conference on Neural Networks, 2015.
  20. S. Thorat & B. Rajendran, Arithmetic Computing via Rate Coding in Neural Circuits with Spike-triggered Adaptive Synapses, International Joint Conference on Neural Networks, 2015.
  21. C. P. Narisetty, K. Saboo & B. Rajendran, Composer Classification based on Temporal Coding in Adaptive Spiking Neural Networks, International Joint Conference on Neural Networks, 2015.
  22. V. Ostwal, R. Meshram, B. Rajendran & U. Ganguly, An ultra-compact and low power neuronbased on SOI platform, International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2015.
  23. C. Shetty, P. Shah, S. Nitchith, R. Rawat, Nandakumar S. R, S. Kulkarni & B. Rajendran, Live Demonstration: Spiking Neural Circuit Based Navigation Inspired by C. elegans Thermotaxis, IEEE International Symposium on Circuits & Systems 2015.
  24. P. J. Nair, C. Chou, B. Rajendran & M. K. Qureshi, Reducing Read Latency of Phase Change Memory via Early Read and Turbo Read, IEEE International Symposium on High-Performance Computer Architecture, 2015.
  25. A. Kothiyal, B. Rajendran & S. Murthy, Delayed Guidance: A teaching-learning strategy to develop ill-structured problem-solving skills in engineering, textitIEEE International Conference on Learning and Teaching in Computing and Engineering, 2015.
  26. A. Anand, A. Kothiyal, B. Rajendran & S. Murthy, Guided Problem Solving, and Group Programming - A Technology-Enhanced Teaching-Learning Strategy for Engineering Problem Solving, IEEE International Conference on Technology for Education, 2014.
  27. N. Panwar, D. Kumar, N. K. Upadhyay, P. Arya, U. Ganguly & B. Rajendran, Memristive Synaptic Plasticity in Pr0:7Ca0:3MnO3 RRAM by Bio-mimetic Programming, Device Research Conference, 2014.
  28. R. Meshram, B. Rajendran & U. Ganguly, Biomimetic 4F2 synapse with intrinsic timescale for pulse-based STDP by I-NPN selection device, Device Research Conference, 2014.
  29. A. Bora, A. Rao and B. Rajendran, Mimicking the worm – an adaptive spiking neural circuit for contour tracking inspired by C. Elegans thermotaxis, textitInternational Joint Conference on Neural Networks, 2014.
  30. A. Singha, B. Muralidharan and B. Rajendran, Analog Memristive Time-Dependent Learning Using Discrete Nanoscale RRAM Devices, International Joint Conference on Neural Networks, 2014.
  31. B. Rajendran, A. K. Henning, B. Cronquist and Z. Or-Bach, Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D ICs, The IEEE International Conference on 3D System Integration, 2013.
  32. A. K. Henning, B. Rajendran, B. Cronquist & Z. Or-Bach, Thermal Considerations for Monolithic Integration of Three-Dimensional Integrated Circuits, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2013.
  33. S. Deshmukh, S. Lashkare, B. Rajendran & U. Ganguly, I-NPN: A sub- 0mV/decade Sub-0.6V selection diode for STTRAM, Device Research Conference, 2013.
  34. M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian & V. Srinivasan, Efficient Scrub Mechanisms for Error-Prone Emerging Memories, IEEE International Symposium on High Performance Computer Architecture, 2012.
  35. J. Seo, B. Brezzo, Y. Liu, B. D. Parker, S. K. Esser, R. K. Montoye, B. Rajendran, J. A. Tierno, L. Chang, D. S. Modha & D. J. Friedman, A 45nm CMOS Neuromorphic Chip with a Scalable Architecture for Learning in Networks of Spiking Neurons, IEEE Custom Integrated Circuits Conference, 2011.
  36. B. Rajendran, R. Cheek, L. Lastras, M. Franceschini, M. Breitwisch, A. Schrott, J. Li, R. Montoye, L. Chang & C. Lam, Demonstration of CAM and TCAM using Phase Change Devices, IEEE International Memory Workshop, 2011.
  37. L. A. Lastras-Montano, M. M. Franceschini, B. Rajendran & C. Lam, Coding for sensing in content addressable memories, IEEE International Symposium on Information Theory, 2010.
  38. B. Rajendran, M. Breitwisch, R. Cheek, M-H. Lee, Y-H. Shih, H-L. Lung & C. Lam, Characterization of Poly-silicon Emitter BJTs as Access Devices for Phase Change Memory, IEEE International Symposium on VLSI Technology, Systems, and Applications, 2009.
  39. Y. H. Shih, M. H. Lee, M. Breitwisch, R. Cheek, J. Y. Wu, B. Rajendran, Y. Zhu, E. K. Lai, C. F. Chen, H. Y. Cheng, A. Schrott, E. Joseph, R. Dasaka, S. Raoux, H. L. Lung & C. Lam, Understanding Amorphous States of Phase-Change Memory Using Frenkel-Poole Model, International Electron Devices Meeting 2009.
  40. C.-F. Chen, A. Schrott, M. H. Lee, S. Raoux, Y. H. Shih, M. Breitwisch, F. H. Baumann, E. K. Lai, T. M. Shaw, P. Flaitz, R. Cheek, E. A. Joseph, S. H. Chen, B. Rajendran, H. L. Lung & C. Lam, Endurance Improvement of Ge2Sb2Te5 based Phase Change Memory, IEEE International Memory Workshop, 2009.
  41. K. Lu, B. Rajendran, T. D. Happ, R. M. Y. Ng, H-L. Lung, C. Lam & M. Chan, Optimized Scaling of Diode Array Design for 32nm Node Phase Change Memory, IEEE International Symposium on VLSI Technology, Systems, and Applications, 2008.
  42. B. Rajendran, J. Karidis, M-H. Lee, M. Breitwisch, G. W. Burr, Y-H. Shih, R. Cheek, A. Schrott, H-L. Lung & C. Lam, Analytical Model for RESET Operation of Phase Change Memory, International Electron Devices Meeting 2008.
  43. B. Rajendran, M-H. Lee, M. Breitwisch, G.W. Burr, Y-H. Shih, R. Cheek, A. Schrott, C-F. Chen, M. Lamorey, E. Joseph, Y. Zhu, R. Dasaka, P. L. Flaitz, F. H. Baumann, H-L. Lung & C. Lam, On the Dynamic Resistance and Reliability of Phase Change Memory, VLSI Technology Symposium 2008.
  44. Y. H. Shih, J. Y. Wu, B. Rajendran, M. H. Lee, R. Cheek, M. Lamorey, M. Breitwisch, Y. Zhu, E. K. Lai, C.F. Chen, E. Stinzianni, A. Schrott, E. Joseph, R. Dasaka, S. Raoux, H. L. Lung & C. Lam, Mechanisms of Retention Loss in Ge2Sb2Te5-based Phase- hange Memory, International Electron Devices Meeting 2008.
  45. T. Nirschl, J. B. Philipp, T. D. Happ, G. W. Burr, B. Rajendran, M. H. Lee, A. Schrott, M. Yang, M. Breitwisch, C. F. Chen, E. Joseph, M. Lamorey, R. Cheek, S.H. Chen, S. Zaidi, S. Raoux, Y. C. Chen, Y. Zhu, R. Bergmann, H. L. Lung & C. Lam, Write Strategies for 2 and 4-bit multi-level Phase Change Memory, International Electron Devices Meeting 2007.
  46. M. Breitwisch, T. Nirschl, C.F. Chen, Y. Zhu, M. H. Lee, M. Lamorey, G. W. Burr, E. Joseph, A. Schrott, J. B. Philipp, R. Cheek, T. D. Happ, S. H. Chen, S. Zaidi, P. Flaitz, J. Bruley, R. Dasaka, B. Rajendran, S. Rossnagel, M. Yang, Y. C. Chen, R. Bergmann, H. L. Lung & C. Lam, Novel Lithography-Independent Pore Phase Change Memory, VLSI Technology Symposium 2007.
  47. B. Rajendran, P. Kapur, K. C. Saraswat & R. F. W. Pease, Power/ Performance/ Reliability Analysis for Copper Interconnects, ACM International Workshop on System Level Interconnect Prediction 2004.
  48. B. Rajendran, V. Kheterpal, A. Das, J. Majumder, C. Mandal & P. P. Chakraborty, Timing Analysis of Tree-like RLC Circuits, IEEE International Symposium on Circuits and Systems 2002.