Patents

  1. D. J. Friedman, S. Kim, C. Lam, D. Modha, B. Rajendran & J. Tierno, Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices, US Patent 9269042.
  2. C. Dubourdieu, M. Frank, B. Rajendran & A. Schrott, Phase change material cell with piezoelectric or ferroelectric stress inducer liner, US Patent 9159920.
  3. T. Happ, H. Lung, B. Rajendran & M. Yang, Integrated circuit including vertical diode, US Patent 9064794.
  4. M. G. Farooq, E. Kursun, G. W. Maier, & B. Rajendran, Phase change memory management, US Patent 9047938.
  5. H-L. Lung, E-K. Lai, C. Lam & B. Rajendran, Polysilicon pillar bipolar transistor with selfaligned memory element, US Patent 8933536.
  6. B. Brezzo, L. Chang, S. Esser, D. Friedman, Y. Liu, D. Modha, R. Montoye, B. Rajendran J. Seo & J. Tierno, Reconfigurable and customizable general-purpose circuits for neural networks, US Patent 8898097.
  7. B. Brezzo, L. Chang, S. Esser, D. Friedman, Y. Liu, D. Modha, R. Montoye, B. Rajendran, J. Seo & J. Tierno, Reconfigurable and customizable general-purpose circuits for neural networks, US Patent 8856055.
  8. B. Rajendran & M. Ritter, Electronic synapses from stochastic binary memory devices US Patent 8832011.
  9. B. Rajendran & M. Ritter, Electronic synapses from stochastic binary memory devices, US Patent 8832010.
  10. S. Kim, Y. Liu & B. Rajendran, Compact low-power asynchronous resistor-based memory read operation and circuit, US Patent 8824218.
  11. M. BrightSky, R. Cheek, C. Lam, E. Joseph, B. Rajendran, A. Schrott, Y. Zhu, Thermally insulated phase change material cells, US Patent 8772906.
  12. M. Breitwisch & B. Rajendran, Phase change memory electrode with sheath for reduced programming current, US Patent 8648326.
  13. B. Rajendran, T. Happ, H-L. Lung & M. Yang, Method for fabrication of crystalline diodes for resistive memories, US Patent 8637844.
  14. M. Breitwisch, C. Lam, D. S. Modha & B. Rajendran, Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks, US Patent 8589320.
  15. T. Happ, H-L Lung, B. Rajendran & M. Yang, Integrated circuit including vertical diode, US Patent 8586960.
  16. C. Dubourdieu, M. M. Frank, B. Rajendran & A. Schrott, Phase change material cell with stress inducer liner, US Patent 8559217.
  17. B. Rajendran, T. Ning & C. Lam, Polysilicon emitter BJT access device for PCRAM, US Patent 8558210.
  18. M. Breitwisch, R. Cheek, E. Joseph, C. Lam, B. Rajendran, A. Schrott, Y. Zhu, Thermally insulated phase change material memory cells, US Patent 8536675.
  19. B. Jackson, D. Modha & B. Rajendran, Producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array, US Patent 8527438.
  20. M. Breitwisch, R. Cheek, E. Joseph, C. Lam, B. Rajendran, A. Schrott & Y. Zhu, thermally insulated phase material cells, US Patent 8466006.
  21. M. Breitwisch, R. Cheek, C. Lam, D. Modha& B. Rajendran, System for electronic learning synapse with spike-timing dependent plasticity using phase change memory, US Patent 8447714.
  22. H-L Lung, C. Lam, M-H. Lee & B. Rajendran, Phase change memory cells having vertical channel access transistor and memory plane, US Patent 8350316.
  23. S. Kim, Y. Liu & B. Rajendran, Compact low-power asynchronous resistor-based memory read operation and circuit, US Patent 8331164.
  24. M. Breitwisch, C. Lam, D. Modha & B. Rajendran, Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material, US Patent 8311965.
  25. B. G. Elmegreen, R. Linsker, D. M, Newns, B. Rajendran & R. D. Traub, Hardware analog-digital neural networks, US Patent 8275727
  26. Y-H. Shih, M-H. Lee, C-I.Wu, H-L. Lung, C-H. Lam, R. Cheek, M. J. Breitwisch & B. Rajendran, Methods and apparatus for reducing defect bits in Phase Change Memory, US Patent 8238149.
  27. H-L. Lung, E-K. Lai B. Rajendran & C. Lam, Polysilicon plug bipolar transistor for phase change memory, US Patent 8237144.
  28. M. Breitwisch, C-H. Lam, B. Rajendran, S. Raoux, A. Schrott & D. Krebs, Phase Change Memory device suitable for high temperature operation, US Patent 8233317.
  29. B. Rajendran, T. H. Ning & C. Lam, Polysilicon Emitter BJT Access Device For PCRAM, US Patent 8217380.
  30. T-C. Chen, C-H. Lam & B. Rajendran, PCM With Poly-Emitter BJT Access Devices, US Patent 8138574.
  31. M. Breitwisch, R. Cheek, E. Joseph, C. Lam, B. Rajendran, A. Schrott& Y. Zhu, Thermally insulated phase change material memory cells with pillar structure, US Patent 8138056.
  32. B. L. Ji, C. Lam, R. K. Montoye & B. Rajendran, Ternary Content Addressable Memory using Phase Change Devices, US Patent 8120937.
  33. S. Bangsaruntip, E. Joseph, C. Lam, B. Rajendran, M. Rothwell & A. Schrott, Nanoscale electrodes for phase change memory devices, US Patent 8119528.
  34. M. Breitwisch, C. Lam & B. Rajendran, Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition, US Patent 8116126.
  35. M. J. Breitwisch, G. S. Ditlow, M. M. Franceschini, L. A. Lastras-Montano, R.K. Montoye & B. Rajendran, Resistive memory devices having a NOT-AND (NAND) structure, US Patent 8107276.
  36. H-L. Lung, E-K. Lai, B. Rajendran & C. Lam, Polysilicon plug bipolar transistor for Phase Change Memory, US Patent 8030635.
  37. H-L. Lung, M. Yang, T. D. Happ & B. Rajendran, Memory array with diode driver and method for fabricating the same, US Patent 8030634.
  38. M. J. Breitwisch, C. H. Lam & B. Rajendran, Phase Change Memory with finite annular conductive path, US Patent 7965537.
  39. B. Rajendran, T. D. Happ, M. Yang & H-L. Lung, Method for fabrication of poly-crystalline diodes for resistive memories, US Patent 7955958.
  40. C. H. Lam, M-H. Lee, T. Nirschl & B. Rajendran, Multi-level cell programming of PCM by varying the reset amplitude, US Patent 7944740.
  41. B. Rajendran, T. Happ, H-L. Lung, Method for fabrication of single crystal diodes for resistive memories, US Patent 7902051.
  42. M. Breitwisch, C. Lam & B. Rajendran, Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition, US Patent 7894272.
  43. M. M. Franceschini, C. Lam, L. A. Lastras & B. Rajendran, Coding techniques for improving the sense margin in content addressable memories, US Patent 7881089, High Value Patent Award from IBM.
  44. C. Lam & B. Rajendran, High density ternary content addressable memory, US Patent 872889.
  45. M. Breitwisch, C. Lam, H-L. Lung, B. Rajendran, A. Schrott & Y. Zhu, Phase change memory device and method of manufacture, US Patent 7868313.
  46. B. Rajendran & S. Zaidi, Integrated circuit including silicide region to inhibit parasitic currents, US Patent 7863610.
  47. C. Lam & B. Rajendran, Process for PCM integration with poly-emitter BJT as access device, US Patent 7811879.
  48. C. Lam & B. Rajendran, High density content addressable memory using phase change devices, US Patent 7782646, High Value Patent Award from IBM.
  49. M. Breitwisch, C. Lam & B. Rajendran, Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition, US Patent 7764533.
  50. C. Lam, B. L. Ji, R. K. Montoye & B. Rajendran, Content addressable memory using Phase Change Devices, US Patent 7751217.
  51. M. Lee, B. Rajendran & C. Lam, Phase change memory dynamic resistance test and manufacturing methods, US Patent 7639527.
  52. C. Lam and B. Rajendran, Method to create a uniformly distributed multi-level cell (MLC) bitstream from a non-uniformly distributed MLC bitsream, US Patent 7606067.
  53. M. Breitwisch, C. Lam & B. Rajendran, Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition, US Patent 7602632.
  54. M. Breitwisch, C. Lam & B. Rajendran, Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition,US Patent 7602631.
  55. M. Breitwisch, C. Lam & B. Rajendran, Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition, US Patent 7567473.
  56. M. Breitwisch, C. Lam & B. Rajendran, Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition. US Patent 7505334.