Patents

  1. M. Breitwisch, C. Lam, & B. Rajendran,  Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition. US Patent  7505334.
  2. M. Breitwisch, C. Lam, & B. Rajendran,  Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition. US Patent 7567473.
  3. M. Breitwisch, C. Lam, & B. Rajendran,  Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition. US Patent 7602631.
  4. M. Breitwisch, C. Lam, & B. Rajendran,  Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition. US Patent 7602632.
  5. C. Lam & B. Rajendran,  Method To Create A Uniformly Distributed Multi-Level Cell (MLC) Bitstream From A Non-Uniformly Distributed MLC Bitsream.  US Patent 7606067. 
  6. M. Lee, B. Rajendran, C. Lam,  Phase Change Memory Dynamic Resistance test and manufacturing methods.  US Patent 7639527. 
  7. C. Lam, B. L. Ji, R. K. Montoye & B. Rajendran,  Content Addressable Memory using Phase Change Devices.  US Patent 7751217. 
  8. C. Lam & B. Rajendran,  High Density Content Addressible Memory using Phase Change Devices.  US Patent 7782646. 
  9. C. Lam & B. Rajendran,  Process for PCM integration with poly-emitter BJT as access device.  US Patent 7811879. 
  10. B. Rajendran & S. Zaidi,  Integrated Circuit Including Silicide Region To Inhibit Parasitic Currents.  US Patent 7863610. 
  11. M. Breitwisch, C. Lam, H-L. Lung, B. Rajendran, A. Schrott & Y. Zhu,  Phase Change Memory device and method of manufacture.  US Patent 7868313. 
  12.  C. Lam & B. Rajendran,  High Density Ternary Content Addressable Memory. US Patent 7872889. 
  13. M. M. Franceschini, C. Lam, L. A. Lastras & B. Rajendran,  Coding techniques for improving the sense margin in content addressable memories.  US Patent 7881089. 
  14. M. Breitwisch, C. Lam, & B. Rajendran,  Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition. US Patent 7894272.
  15. B. Rajendran, T. Happ, H-L. Lung,  Method for fabrication of single crystal diodes for resistive memories.  US Patent 7902051. 
  16. C. H. Lam, M-H. Lee, T. Nirschl & B. Rajendran,  Multi-level cell programming of PCM by varying the reset amplitude.  US Patent 7944740. 
  17. B. Rajendran, T. D. Happ, M. Yang & H-L. Lung,  Method for fabrication of poly-crystalline diodes for resistive memories.  US Patent 7955958. 
  18. M. J. Breitwisch, C. H. Lam & B. Rajendran,  Phase Change Memory with finite annular conductive path.  US Patent 7965537. 
  19. H-L. Lung, M. Yang, T. D. Happ & B. Rajendran,  Memory array with diode driver and method for fabricating the same. US Patent 8030634. 
  20. B. Rajendran, T. Ning & C. Lam. Polysilicon emitter BJT access device for PCM. Chinese Patent ZL200910002016.5
  21. H-L. Lung, E-K. Lai, B. Rajendran & C. Lam,  Polysilicon plug bipolar transistor for Phase Change Memory.  US Patent 8030635. 
  22. M. J. Breitwisch, G. S. Ditlow, M. M. Franceschini, L. A. Lastras-Montano, R.K. Montoye & B. Rajendran. Resistive memory devices having a NOT-AND (NAND) structure. US Patent 8107276.
  23. M. Breitwisch, C. Lam, & B. Rajendran,  Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition. US Patent  8116126.
  24. S. Bangsaruntip, E. Joseph, C. Lam, B. Rajendran, M. Rothwell & A. Schrott. Nanoscale electrodes for phase change memory devices. US Patent 8119528.
  25. B. L. Ji, C. Lam, R. K. Montoye & B. Rajendran. Ternary Content Addressable Memory using Phase Change Devices. US Patent 8120937
  26. M. J. Breitwisch, R. Cheek, E. Joseph, C. Lam, B. Rajendran, A. Schrott & Y. Thermally insulated phase change material memory cells with pillar structure. US Patent 8138056.
  27. T-C. Chen, C-H. Lam & B. Rajendran. PCM With Poly-Emitter BJT Access Devices. US Patent 8138574.
  28. B. Rajendran, T. H. Ning & C. Lam. Polysilicon Emitter BJT Access Device For PCRAM. US Patent 8217380
  29. M. Breitwisch, C-H. Lam, B. Rajendran, S. Raoux, A. Schrott & D. Krebs. Phase Change Memory device suitable for high temperature operation. US Patent 8233317.
  30. H-L. Lung, E-K. Lai B. Rajendran & C. Lam. Polysilicon plug bipolar transistor for phase change memory. US Patent 8237144.
  31. Y-H. Shih, M-H. Lee, C-I. Wu, H-L. Lung, C-H. Lam, R. Cheek, M. J. Breitwisch & B. Rajendran. Methods and apparatus for reducing defect bits in Phase Change Memory. US Patent 8238149
  32. B. G. Elmegreen, R. Linsker, D. M, Newns, B. Rajendran & R. D. Traub. Hardware analog-digital neural networks. US Patent 8275727
  33. M. Breitwisch, C. Lam, D. Modha & B. Rajendran. Area efficient neuromorphic circuits using field efect transistors (FET) and variable resistance material. US Patent 8311965
  34. S. Kim, Y. Liu  & B. Rajendran. Compact low-power asynchronous resistor-based memory read operation and circuit. US Patent 8331164
  35. H-L Lung, C. Lam, M-H. Lee & B. Rajendran. Phase change memory cells having vertical channel access transistor and memory plane. US Patent 8350316.
  36. M. Breitwisch, R. Cheek, C. Lam, D. Modha & B. Rajendran.  System for electronic learning synapse with spike-timing dependent plasticity using phase change memoryUS Patent 8,447,714.
  37. M. Breitwisch, R. Cheek, E. Joseph, C. Lam, B. Rajendran, A. Schrott & Y. Zhu, Thermally insulated phase material cells. US Patent 8,466,006.
  38. B. Jackson, D. Modha & B. Rajendran. Producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array. US Patent 8,527,438
  39. B. Rajendran, T. Ning & C. Lam. Polysilicon emitter BJT access device for PCRAM. US Patent 8,558,210
  40. C. Dubourdieu, M. M. Frank , B. Rajendran & A. Schrott. Phase change material cell with stress inducer liner. US Patent 8,559,217.
  41. T. Happ, H-L Lung, B. Rajendran & M. Yang. Integrated circuit including vertical diode. US Patent 8,586,960.
  42. M. Breitwisch, C. Lam, D. S. Modha  &  B. Rajendran. Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks.    US Patent 8,589,320. 
  43. B. Rajendran, T. Happ, H-L. Lung & M. Yang. Method for fabrication of crystalline diodes for resistive memories. US Patent 8,637,844
  44. M. Breitwisch & B. Rajendran. Phase change memory electrode with sheath for reduced programming current. US Patent 8,648,326
  45. M. BrightSky, R. Cheek, C. Lam, E. Joseph, B. Rajendran, A. Schrott, Y. Zhu. Thermally insulated phase change material cells. US Patent 8772906
  46. S. Kim, Y. Liu & B. Rajendran. Compact low-power asynchronous resistor-based memory read operation and circuit. US Patent 8824218
  47. B. Rajendran & M. Ritter. Electronic synapses from stochastic binary memory devices. US Patent 8832010
  48. B. Rajendran & M. Ritter. Electronic synapses from stochastic binary memory devices. US Patent 8832011
  49. B. Brezzo, L. Chang, S. Esser, D. Friedman, Y. Liu, D. Modha, R. Montoye, B. Rajendran, J. Seo & J. Tierno. Reconfigurable and customizable general-purpose circuits for neural networks. US Patent 8856055.
  50. B. Brezzo, L. Chang, S. Esser, D. Friedman, Y. Liu, D. Modha, R. Montoye, B. Rajendran, J. Seo & J. Tierno. Reconfigurable and customizable general-purpose circuits for neural networks. US Patent 8898097.
  51. H-L. Lung, E-K. Lai, C. Lam & B. Rajendran. Polysilicon pillar bipolar transistor with self-aligned memory element. US Patent 8933536.
  52. M. G. Farooq, E. Kursun, G. W. Maier, & B. Rajendran. Phase change memory management. US Patent 9047938.
  53. T. Happ, H. Lung, B. Rajendran & M. Yang. Integrated circuit including vertical diode. US Patent 9064794.
  54. C. Dubourdieu, M. Frank, B. Rajendran & A. Schrott. Phase change material cell with piezoelectric or ferroelectric stress inducer liner. US Patent 9159920
  55. D. J. Friedman, S. Kim, C. Lam, D. Modha, B. Rajendran & J. Tierno. Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices. US Patent 9269042