Data size and functionality requirements for computing are increasing, according to the expectation that hardware performance will continue to improve, irrespective of the actual implementation. This is particularly true for emerging distributed computing paradigms for the Internet of Things, such as Edge Computing and Fog Computing, which are placing extraordinarily stringent constraints on computing hardware performance. Such paradigms are necessary to guarantee low‐latency, secure and contextualized computation on inhomogeneous sensory data, as close as possible to the data source. This usually implies that energy sources are limited and consequently, that Edge Computing hardware energy efficiency must be maximized. At the system level, it is widely accepted that reconfigurable logic hardware can significantly reduce energy per computation, particularly as the problem size increases. Such hardware can be placed in the data acquisition chain between the raw sensor output and the central computing core and given the task of pre‐processing the data in order to reduce the core workload. It can also be placed in the data processing chain between the memory banks and the central computing core to accelerate specific computation tasks, reducing latency and energy costs. Therefore, the use of energy‐efficient, reconfigurable hardware accelerators is mandatory to unlock the full potential of Edge Computing.
In this context, the emergence of new research devices offers the opportunity to provide novel building blocks, to elaborate non-conventional techniques for logic design and consequently to reconsider the paradigms of computing architectures (such as approximate computing, stochastic computing, and neuromorphic computing) to achieve orders of magnitude improvements in the conventional figure of merit (MIPS / volume*power). Highlights of previous work, based on specifically exploiting the additional functionality of 4-terminal devices for reconfigurability purposes include:
design and patenting of ultra-fine grain reconfigurable architectures and cells based on ambipolar double-gate CNTFETs and on double-gate MOSFETs
development and patenting of interconnect topologies and architectures based on reconfigurable cells
development of logic synthesis techniques for ambipolar reconfigurable logic and mapping and synthesis flows for matrix-based architectures
Currently funded work is focusing on:
building new 3D logic circuit architectures based on vertical nanowire FETs. Such devices favor regular logic structures with multiple switches in series based on techniques such as majority gate logic or pass‐gate logic. This work therefore aims to prove enhanced logic functionality and logic circuit operation in terms of propagation delay, dynamic and static power consumption, resilience to temperature and supply voltage variation, and to assess the technology roadmap improvements and the associated logic performance metrics.
exploring low-power logic cell architectures based on ferroelectric capacitors and FETs (FeFETs). HfO2-based ferroelectric non-volatile devices are CMOS-compatible, fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This will give unprecedented flexibility for fine-grain logic-in-memory (LiM) circuits, which allows data storage close to logic circuits, reduces energy cost of data transfer, allows smart gating for "normally-off" computing and opens the way to real demonstration of novel energy-efficient computing paradigms.
This work is the result of 6 PhD theses (2 ongoing) and 4 postdocs, supported by several projects at the national level (ACI Nanosys, ANRARPEGE Nanograin, ANRPNANO Multigrilles, LST Grilles-CMOS, ANRAAPG LEGO) and at the European level (H2020-ICT 3eFerro, H2020-FETPROACT FVLLMONTI, Horizon Europe Ferro4EdgeAI).
Collaborations: CEA-LETI (FR), IMS (FR), IM2NP (FR), LIRMM (FR), IEF (FR), IEMN (FR), UMP CNRS-Thales (FR), LAAS (FR), NaMLab (DE), EPFL (CH), Ecole Polytechnique de Montréal (CA), Global TCAD Solutions (AT).