I. O'Connor, A. Kaiser, "Automated design of switched-current cells," Proc. Custom Integrated Circuits Conference, pp. 477-480, Santa-Clara (USA), May 1998

B. Stefanelli, I. O'Connor, L. Quiquerez, A. Kaiser, D. Billet, "An analog beam-forming circuit using switched-current delay lines," Proc. European Solid-State Circuits Conference, pp. 300-303, The Hague (Netherlands), Sep. 1998

P. Bontoux, I. O'Connor, F. Gaffiot, G. Jacquemod, "Design and optimization of passive components for optical interconnects," DTIP'2000, Paris, May 9-11, 2000

P. Bontoux, F. Mieyeville, I. O'Connor, F. Gaffiot, G. Jacquemod, "Design and optimization of optical links based on VHDL-AMS modeling," BMAS'2000, Orlando, FL, USA, October 19-20, 2000, p.62-67

F. Mieyeville, G. Jacquemod, I. O'Connor, F. Gaffiot, "Behavioral modeling of short distance optical interconnects," ISMA 2000, Singapore, 27 November-2 December 2000, SPIE Proceedings vol. 4228, n° 02, pp. 1-8

I. O'Connor, F. Mieyeville, F. Tissafi-Drissi, F. Gaffiot, "Exploration paramétrique d'amplificateurs de transimpédance CMOS à bande passante maximisée," Colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications, Paris, France, Sept. 2002

F. Mieyeville, F. Gaffiot, I. O'Connor, J. Oudinot, P. Raynaud, F Mkalech, "VCSEL-based Optical Communication Link Simulation using VHDL-AMS," DATE 2003, Exhibition forum, Session X

M. Brière, F. Gaffiot, I. O'Connor, L. Carrel, "Integration of an FDTD algorithm in an electronic design framework," 5th International Workshop on Computational Electromagnetics, pp. 21-26, Halifax, Canada, 17-19 June 2003

F. Tissafi-Drissi, I. O'Connor, F. Mieyeville, F. Gaffiot, "Design methodologies for high-speed CMOS photoreceiver front-ends," 16th Symposium On Integrated Circuits And System Design, pp. 323-328, Sao Paolo, Brazil, 8-11 September 2003

G. Tosik, F. Gaffiot, Z. Lisik, I. O'Connor, F. Tissafi-Drissi, "Optical versus metallic interconnections for clock distribution networks in new VLSI technologies," 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2003, pp. 461-470, Torino, Italy, 10-12 September 2003

G. Tosik, F. Gaffiot, Z. Lisik, I. O'Connor, "Optical versus Electrical Clock System in Future VLSI Technologies," IEEE International SOC Conference, pp. 261-262, Portland, USA, 17-20 September 2003

F. Mieyeville, M. Brière, I. O'Connor, F. Gaffiot, G. Jacquemod, "A VHDL-AMS library of hierarchical optoelectronic device models," Forum on Specification and Design Languages, pp. 7-18, Frankfurt, Germany, 23-26 September 2003

F. Tissafi-Drissi, I. O'Connor, F. Mieyeville, F. Gaffiot, "Hierarchical synthesis of high-speed CMOS photoreceiver front-ends using a multi-domain behavioral description language," Forum on Specification and Design Languages, pp. 151-162, Frankfurt, Germany, 23-26 September 2003

F. Tissafi-Drissi, I. O'Connor, F. Mieyeville, G. Tosik, F. Gaffiot, "Méthodologie de conception d'un photo-récepteur CMOS à haut-débit," Colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications, pp. 119-122, Louvain-la-Neuve, Belgium, 25-26 Sept. 2003

M. Brière, F. Mieyeville, I. O'Connor, F. Gaffiot, "Un réseau d'interconnexion optique passif basé sur le routage en longueur d'onde," Symposium en Architecture et Adéquation Algorithme Architecture, pp. 425-432, La Colle-sur-Loup, France, 15-17 Oct. 2003

I. O'Connor, F. Mieyeville, F. Tissafi-Drissi, G. Tosik, F. Gaffiot, "Predictive Design Space Exploration of Maximum Bandwidth CMOS Photoreceiver Preamplifiers," IEEE International Conference on Electronics, Circuits and Systems, pp. 483-486, Sharjah, United Arab Emirates, 14-17 December 2003 

F. Tissafi-Drissi, I. O'Connor, F. Gaffiot, "RUNE: Platform for automated design of integrated multi-domain systems. Application to high-speed CMOS photoreceiver front-ends," Design Automation and Test in Europe, pp. 16-21, Paris, France, 16-20 February 2004

G. Tosik, Z. Lisik, M. Langer, F. Gaffiot, I. O'Connor, "Simulation of Electrical and Optical Interconnections for Future VLSI ICs," International Conference on Computational Science, pp.1037-1044, Krakow, Poland, 6-9 June 2004

M. Brière, L. Carrel, T. Michalke, F. Mieyeville, I. O'Connor, F. Gaffiot, "Design and behavioral modeling tools for optical networks on chip," Design Automation and Test in Europe, pp. 738-739, Paris, France, 16-20 February 2004

E. Drouard, M. Brière, F. Mieyeville, I. O'Connor, X. Letartre and F. Gaffiot, "Optical Network On-chip Multi-Domain modeling using SystemC," Proc. Forum on Specification and Design Languages, pp. 123--134, Lille, France, 14-17 September 2004

M. Brière, E. Drouard, F. Tissafi-Drissi, F. Mieyeville, I. O'Connor and F. Gaffiot, "SystemC modeling of an Optical Network-on-Chip using VCI protocol," Proc. GSPx, Santa Clara, CA, USA, September 2004

E. Drouard, M. Brière, A. Kazmierczak, X. Letartre, I. O'Connor, F. Gaffiot, "Phenomenological modeling of WDM crossbars based on channel drop filters," 13th International Workshop on Optical Waveguide Theory and Numerical Modeling (OWTNM 2005), 8 – 9 April 2005, Grenoble

A. Kazmierczak, M. Brière, E. Drouard, P. Rojo-Romeo, I. O'Connor, X. Letartre, F. Gaffiot, L. El Melhaoui, P. Lyan, J.M. Fedeli, "Design and characterization of optical networks on chip," 12th European Conference on Integrated optics (ECIO 2005), 6 – 8 April 2005, Grenoble

M. Brière, E. Drouard, F. Mieyeville, D. Navarro, I. O'Connor, F. Gaffiot, "Heterogeneous modeling of an optical network on chip with SystemC," Proc. IEEE International Workshop on Rapid System Prototyping, pp. 10-16, Montreal, Canada, 8-10 June 2005

M. Owczarek, I. O'Connor, "Program RUNE as an Example of Usage of Computers in Optimization Processes," International Conference Microtherm, Lodz (Poland), 19-22 June 2005

I. O'Connor, F. Tissafi-Drissi, G. Revy, F. Gaffiot, "UML/XML-based approach to hierarchical AMS synthesis," Proc. Forum on Design Languages, pp. 89-100, Lausanne, Switzerland, September 27-30 2005

D. Navarro, D. Ramat, F. Mieyeville, I. O'Connor, F. Gaffiot, "VHDL & VHDL-AMS modeling and simulation of a CMOS imager IP," Proc. Forum on Design Languages, pp. 179-182, Lausanne, Switzerland, September 27-30 2005

D. Navarro, M. Brière, I. O'Connor, F. Mieyeville, F. Gaffiot, L. Carrel, "Quantitative study of area and power consumption costs for 3 Gbits/s optical communications in a 0.13µm CMOS circuit," 20th Conference on Design of Circuits and Integrated Systems, Lisbon, Portugal, 23–25 November 2005

B. Payet, P. Vincent, I. O'Connor, F. Gaffiot, "A fully-integrated 60 GHz VCO in l3Onm SOI-CMOS on high-resistivity substrate," Ph. D. Research in Microelectronics and Electronics (PRIME), pp. 105-108, Otranto (Lecce), Italy, 12-15 June 2006

S. Dia, F. Mieyeville, I. O'Connor, F. Gaffiot, "Modeling and simulation of radiofrequency circuit blocks for performance evaluation in a system-on-chip context," Int. Symp. Performance Evaluation of Computer and Telecommunication Systems, Calgary, Canada, July 31-August 2, 2006

S. Dia, F. Mieyeville, I. O'Connor, F. Gaffiot, "Radio-frequency link modeling and simulation in a system-on-chip context," European Modeling Symposium, London, United Kingdom, 11-12 September 2006

M. Owczarek, G. Tosik, Z. Lisik, I. O'Connor, "Optimization of the On-Chip Optical Receivers," IXth International Conference CADSM, pp. 130-133, Polyana (Ukraine), 20-24 February 2007

M. Brière, B. Girodias, Y. Bouchebaba, G. Nicolescu, F. Mieyeville, F. Gaffiot, I. O'Connor, "System Level Assessment of an Optical NoC in an MPSoC Platform," Design Automation and Test in Europe (DATE), Nice, France, 16-20 April 2007

J. Liu, I. O'Connor, D. Navarro, F. Gaffiot, "Design of a Novel CNTFET-based Reconfigurable Logic Gate," IEEE Symp. VLSI, Porto Alegre, Brazil, 9-11 May 2007

J. Liu, I. O'Connor, D. Navarro, F. Gaffiot, "Novel CNTFET-based Reconfigurable Logic Gate Design," Design Automation Conference (DAC), San Diego, CA, USA, 4-8 June 2007

M. Brière, L. Gheorghe, G. Nicolescu, I. O'Connor, "Formalization of Optical Networks on Chip using DEVS Formalism," Summer Computer Simulation Conference, 14-19 July 2007, San Diego, CA, USA

J. Liu, I. O'Connor, D. Navarro, F. Gaffiot, "Design of a Family of Novel CNTFET-based Dynamically Reconfigurable Logic Gates," IEEE-MWSCAS/NEWCAS Conference, August 5-8, 2007, Montreal, Canada, pp. 698-701

I. Hassoune, I. O'Connor, D. Navarro, "On the performance of Double-Gate MOSFET circuit applications," IEEE-MWSCAS/NEWCAS Conference, August 5-8, 2007, Montreal, Canada, pp. 558-561

M. Brière, B. Girodias, Y. Bouchebaba, G. Nicolescu, F. Mieyeville, F. Gaffiot, I. O'Connor, "Architectural Exploration of Optical and Electrical Interconnects in MPSoC," IEEE-MWSCAS/NEWCAS Conference, August 5-8, 2007, Montreal, Canada, pp. 1469-1472

M. Brière, L. Gheorghe, G. Nicolescu, I. O'Connor, "Towards the High-Level Design of Optical Networks-on-Chip: Formalization of Opto-Electrical Interfaces," IEEE International Conference on Electronics, Circuits and Systems, 11-14 December 2007, Marrakech, Morocco

I. Hassoune, X. Yang, I. O'Connor, D. Navarro, "Using SOI Double-Gate MOSFET NDR Structures to Improve Ultra-Low Power Full Adder Performance," IEEE-NEWCAS/TAISA Conference, June 22-25, 2008, Montreal, Canada

I. Hassoune, I. O'Connor, D. Navarro, "Design of a Family of Gate-level Reconfigurable Logic Cells Based on Double-Gate MOSFETs," 16th IFIP/IEEE Int. Conf. on Very Large Scale Integration (VLSI-SoC), October 13-15 2008, Rhodes Island, Greece

J. Liu, I. O'Connor, D. Navarro and F. Gaffiot, "Dynamically reconfigurable CNTFET logic cell matrix programming methods," 16th IFIP/IEEE Int. Conf. on Very Large Scale Integration (VLSI-SoC), October 13-15 2008, Rhodes Island, Greece

I. O'Connor, F. Mieyeville, F. Gaffiot, A. Scandurra, G. Nicolescu, "Reduction methods for adapting optical network on chip topologies to specific routing applications," Design of Circuits and Integrated Systems (DCIS), November 12-14 2008, Grenoble, France

A. Scandurra, I. O’Connor, "Scalable CMOS-compatible photonic routing topologies for versatile networks on chip," International Workshop on Network on Chip Architectures (NocArc), November 8th 2008, Lake Como, Italy

H. Filiol, I. O'Connor, D. Morche, "A new approach for variability analysis of analog ICs," IEEE-NEWCAS/TAISA Conference, June 29 – July 1, 2009, Toulouse, France

P.E. Gaillardon, I. O’Connor, J. Liu, R. Daviot, N. Abouchi, F. Clermidy, "Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), July 30-31 2009, San Francisco (CA), USA

H. Filiol, I. O'Connor, D. Morche, "Piecewise-Polynomial Modeling for Analog Circuit Performances", European Conference on Circuit Theory & Design (ECCTD'09), 23-27 August 2009, Antalya, Turkey

L. Gheorghe Iugan, G. Nicolescu, I. O’Connor, “Modeling and Formal Verification of a Passive Optical Network on Chip Behavior,” Proc. 3rd International Workshop on Multi-Paradigm Modeling (MPM 2009), 6 October 2009, Denver (CO), USA

P.E. Gaillardon, I. O’Connor, J. Liu, R. Daviot, N. Abouchi, F. Clermidy, "Mapping Method of Reconfigurable Cell Matrices Based on Nanoscale Devices Using Inter-Stage Fixed Interconnection Scheme," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 13-16 December 2009, Hammamet, Tunisia

P.E. Gaillardon, F. Clermidy, I. O'Connor, R. Daviot, "Reconfigurable logic cells for nanoscale – Comparison between density and functionality enhancement," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 13-16 December 2009, Hammamet, Tunisia

A. Allam, I. O'Connor, "Optical NOC Design-Parameters Exploration and Analysis," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 13-16 December 2009, Hammamet, Tunisia

O. Valorge, F. Calmon, M. Le Berre, C. Gontrand, E. Eid, T. Lacrevaz, F. Flechet, J. Charbonnier, I. O’Connor, CEM 2010 "Modélisation RLCG de lignes coplanaires sur un substrat silicium avec couche épitaxiée pour applications CMOS", Colloque International sur la Compatibilité Electromagnétique, 7-9 April 2010, Limoges, France

H. Filiol, I. O’Connor, D. Morche, "Variability Analysis of ICs using the Cornish-Fisher Approximation," European Workshop on CMOS Variability (VARI), May 26-27 2010, Montpellier, France

A. Allam, I. O’Connor, W. Heirman, "Performance Evaluation for Passive-Type Optical Network-on-Chip," IEEE International Symposium on Rapid System Prototyping (RSP), June 8-11 2010, Fairfax (VA), USA 

K. Jabeur, D. Navarro, I. O’Connor, P.E. Gaillardon, M.H. Ben Jamaa, F. Clermidy, "Reducing transistor count in clocked standard cells with ambipolar double-gate FETs," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), July 17-18 2010, Anaheim (CA), USA

B. Wang, L. Labrak, I. O’Connor, E. Drouard, “Bottom-up Verification Methodology for CMOS Photonic Linear Heterogeneous System,” Forum on specification & Design Languages (FDL 2010), September 14-16 2010, Southampton, UK

F. Yengui, L. Labrak, F. Frantz, I. O’Connor, T. Tixier, N. Abouchi, “Comparison of hybrids PSO-SQP and GA-SQP For Transimpedance Amplifier and Optical Driver,” Int. Conf. Metaheuristics and Nature Inspired Computing (META’10), October 27-30 2010, Djerba, Tunisia

P.E. Gaillardon, M.H. Ben-Jamaa, M. Reyboz, G.B. Beneventi, F. Clermidy, L. Perniola, I. O'Connor, "Phase-Change-Memory-Based Storage Elements for Configurable Logic," Int. Conf. Field-Programmable Technology (FPT'10), December 8-10 2010, Beijing, China

B. Wang, I. O’Connor, E. Drouard, "Passive Component Modeling for Optical Network-on-Chip," Asia Communications & Photonics Conference & Exhibition (ACP 2010), December 8-12 2010, Shanghai, China

I. O'Connor, K. Jabeur, D. Navarro, N. Yakymets, P.E. Gaillardon, M.H. Ben-Jamaa, F. Clermidy, "Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics," IEEE Int. Conf. Electronics, Circuits, and Systems (ICECS), 12-15 December 2010, Athens, Greece 

M. H. Ben Jamaa, P. E. Gaillardon, S. Frégonèse, M. De Marchi, G. De Micheli, T. Zimmer, I. O’Connor, F. Clermidy, "FPGA Design with Double-Gate Carbon Nanotube Transistors," China Semiconductor Technology International Conference (CSTIC), 13-14 March 2011, Shanghai, China

S. Le Beux, J. Trajkovic, G. Nicolescu, G. Bois, P. Paulin, I. O’Connor, "Optical ring network-on-chip (ORNOC) architecture and design methodology," Design Automation and Test in Europe (DATE) 2011, 14-18 March 2011, Grenoble, France

A. Fourmigue, G. Beltrame, G. Nicolescu, E.M. Aboulhamid, I. O'Connor, "Multi-granularity thermal evaluation of 3D MPSOC architectures," Design Automation and Test in Europe (DATE) 2011, 14-18 March 2011, Grenoble, France

K. Jabeur, N. Yakymets, I. O'Connor, S. Le Beux, "Fine-Grain Reconfigurable Logic Cells Based on Double-gate CNTFETs," IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI) 2011, 2-4 May 2011, Lausanne, Switzerland

P.E. Gaillardon, M. H. Ben-Jamaa, F. Clermidy, I. O’Connor, "Evaluation of a Crossbar Multiplexer in a Lithography-Based Nanowire Technology," IEEE International Symposium on Circuits and Systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil

N. Yakymets, K. Jabeur, I. O'Connor, S. Le Beux, "Interconnect Topology for Cell Matrices Based on Low-Power Nanoscale Devices," Faible Tension Faible Consommation (FTFC), 30 May – 1 June 2011, Marrakech, Morocco

P.E. Gaillardon, M. H. Ben-Jamaa, F. Clermidy, I. O’Connor, "Can we go towards true 3D architectures?" ACM Design Automation Conference (DAC), San Diego (CA), USA, 6-10 June 2011

P.E. Gaillardon, M. H. Ben-Jamaa, F. Clermidy, I. O’Connor, "Ultra-Fine Grain FPGAs: A Granularity Study", IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), San Diego (CA), USA, 8-9 June 2011

K. Jabeur, N. Yakymets, I. O'Connor, S. Le Beux, "Ambipolar double-gate FET binary-decision diagram (Am-BDD) for reconfigurable logic cells," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), San Diego (CA), USA, 8-9 June 2011

D. Navarro, F. Mieyeville, W. Du, M. Galos, I. O'Connor, "Towards a Design Framework for Heterogeneous Wireless Sensor Networks," International Symposium on Access Spaces (IEEE-ISAS), Yokohama, Japan, 17-19 June 2011

N. Yakymets, K. Jabeur, I. O'Connor, S. Le Beux, "Mapping Methodology and Analysis of Matrix-Based Nanocomputer Architectures," 9th IEEE International NEWCAS Conference, Bordeaux, France, 26-29 June 2011 (Recipient of Best Paper Award)

V. Viswanathan, L. Labrak, F. Frantz, D. Navarro and I. O’Connor, "Model based design of imager using abstraction-segregated parameter dependency graphs," 9th IEEE International NEWCAS Conference, Bordeaux, France, 26-29 June 2011

M. Galos, D. Navarro, F. Mieyeville, I. O'Connor, "Energy-Aware Software Updates in Heterogeneous Wireless Sensor Networks," 9th IEEE International NEWCAS Conference, Bordeaux, France, 26-29 June 2011

F. Frantz, L. Labrak, I. O'Connor, "3D-IC Floorplanning: Applying Meta-Optimization to Improve Performance," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Hong Kong, China, 3-5 October 2011

M. Galos, D. Navarro, F. Mieyeville, I. O'Connor, "Reprogramming hardware-software heterogeneous Wireless Sensor Networks," 14th International Symposium on Wireless Personal Multimedia Communications (WPMC), Brest, France, 3-6 October 2011

W. Du, D. Navarro, F. Mieyeville, I. O'Connor, "IDEA1: A Validated System-level Simulator for Wireless Sensor Networks," 4th International Workshop on Wireless Sensor, Actuator and Robot Networks (WiSARN-FALL 2011), Valencia, Spain, 17-22 October 2011

H. Zhu, S. Le Beux, I. O'Connor, "Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-Based Architectures;" International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 30 November – 2 December 2011

D. Navarro, Z. Feng, V. Viswanathan, L. Carrel, I. O'Connor, "Image toolbox for CMOS image sensors simulations in Cadence ADE," International Conference on Design and Modeling in Science, Education, and Technology (DeMset), Orlando (FL), USA, 29 November – 2 December 2011

K. Jabeur, I. O'Connor, N. Yakymets, S. Le Beux, "High Performance 4:1 Multiplexer with Ambipolar Double-Gate FETs," IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Beirut, Lebanon, 11-14 December 2011

A. Allam, I. O'Connor, "A Protocol Stack Architecture for Optical Network-on-Chip," International Conference on Computing and Information Technology, Al-Madinah Al-Munawwarah, Saudi Arabia, 12-14 March 2012

K. Jabeur, I. O'Connor, N. Yakymets, S. Le Beux, "Ambipolar double-gate FETs for the design of compact logic structures," IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI) 2012, Salt Lake City (UT), USA, 3-4 May 2012

M. Galos, D. Navarro, F. Mieyeville, I. O'Connor, “A cycle-accurate transaction-level modeled energy simulation approach for heterogeneous Wireless Sensor Networks,” IEEE 10th International New Circuits and Systems Conference (NEWCAS), pp. 209–212, Montreal, Canada, 17-20 June 2012

K. Jabeur, I. O'Connor, D. Navarro, S. Le Beux, "Low-power design technique with ambipolar double gate devices," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), Amsterdam, Netherlands, 4-6 July 2012

K. Jabeur, I. O'Connor, S. Le Beux, D. Navarro, "Ambipolar double gate CNTFET based reconfigurable logic cells," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), Amsterdam, Netherlands, 4-6 July 2012

Z. Feng, V. Viswanathan, D. Navarro, I. O’Connor, “Image sensor matrix high speed simulation,” WASET International Conference on Electronics, Circuits, and Systems (ICECS), Venice, Italy, 14-16 November 2012

N. Zhu, I. O'Connor, "Energy Performance of High Data Rate and Low Power Transceiver based Wireless Body Area Networks," Int. Conf. Sensor Networks (Sensornets), pp. 141-144, Barcelona, Spain, 19-22 February 2013

Z. Li, S. Le Beux, C. Monat, X. Letartre, I. O’Connor, “Optical Look Up Table,” Design Automation and Test in Europe (DATE) 2013, Grenoble, France, 18-22 March 2013

N. Zhu, I. O’Connor, “Energy Measurements and Evaluations on High Data Rate and Ultra Low Power WSN Node,” IEEE International Conference on Networking Sensing and Control (ICNSC), pp. 232-236, Paris, France, 10-12 April 2013

P. Coudrain, D. Henry, A. Berthelot, J. Charbonnier, S. Verrun, R. Franiatte, N. Bouzaida, G. Cibrario, F. Calmon, I. O'Connor, T. Lacrevaz, L. Fourneaud, B. Flechet, N. Chevrier, A. Farcy, O. Le-Briz, "3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies," IEEE Electronic Components and Technology Conference (ECTC), pp. 674-382, Las Vegas (NV), USA, 28-31 May 2013 

N. Zhu, I. O’Connor, "Performance evaluations of unslotted CSMA/CA algorithm at high data rate WSNs scenario," 9th IEEE International Wireless Communications and Mobile Computing Conference (IWCMC), pp. 406-411, Cagliari, Italy, 1-5 July 2013

K. Cheng, S. Le Beux, I. O'Connor, "Am/IDG-FET based Reconfigurable Cells versus LUTs: Characteristics Description and Analysis," 25th IEEE Int. Conf. Microelectronics (ICM), Beirut, Lebanon, pp. 1-4, 15-18 December 2013

R. Cao, L. Couder, J. Cayo, J. Ferguson, F. Pikus, A. Arriordaz, I. O’Connor, “Curvilinear Property Measurement and Computation Methods for Physical Verification of Bent Waveguides in Photonic Integrated Circuit Layouts,” IEEE Optical Interconnects Conference, San Diego, 20-22 April 2014

S. Le Beux, F. Alibart, D. Vuillaume, C. Dubourdieu, I. O’Connor, "Memristive devices: an interconnect solution for matrix-based architectures?" Symposium S: Memristor materials, mechanisms and devices for unconventional computing, E-MRS 2014 Spring Meeting, Lille, France, 26-30 May 2014

R. Cao, J. Ferguson, Y. Drissi, F. Gays, A. Arriordaz, I. O’Connor, "DRC Challenges and Solutions for Non-Manhattan Layout Designs," International Conference on Optical MEMS and Nanophotonics (OMN), Glasgow, UK, 17-21 August 2014

R. Cao, H. Hu, J. Ferguson, F. Pikus, J. Cayo, A. Arriordaz, E. Cassan, W. Bogaerts, I. O’Connor, “Photonics Design with an EDA approach : Validation of Layout Waveguide Interconnects,” IEEE 11th International Conference on Group IV Photonics (GFP), Paris, France, 27-29 August 2014

R. Cao, J. Ferguson, F. Gays, Y. Drissi, A. Arriordaz, I. O’Connor, “Silicon Photonics Design Rule Checking : Application of a Programmable Modeling Engine for Non-Manhattan Geometry Verification,” IEEE/IFIP 22nd International Conference on VLSI and System-on-Chip (VLSI-SoC), Playa del Carmen, Mexico, 6-8 October 2014

Z. Li, S. Le Beux, C. Monat, I. O'Connor, X. Letartre, "Complementary logic interface for high performance optical computing with OLUT," IEEE/IFIP 22nd International Conference on VLSI and System-on-Chip (VLSI-SoC), Playa del Carmen, Mexico, 6-8 October 2014

J. Luo, C. Killian, S. Le Beux, D. Chillet, H. Li, I. O'Connor, O. Sentieys, "Channel Allocation protocol for reconfigurable Optical Network-on-Chip," Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing (SiPhotonics), Amsterdam, The Netherlands, 19-21 January 2015

H. Li, S. Le Beux, I. O’Connor, G. Nicolescu, "Energy-Efficient Optical Crossbars on Chip with Multi-Layer Deposited Silicon," 20th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 19-22 January 2015

H. Li, A. Fourmigue, S. Le Beux, X. Letartre, I. O’Connor, G. Nicolescu, "Thermal-Aware Design Method for On-Chip Optical Interconnect," Design Automation and Test in Europe (DATE) 2015, Grenoble, France, 9-13 March 2015

R. Cao, J. Billoudet, J. Ferguson, L. Couder, J. Cayo, A. Arriordaz, I. O’Connor, "LVS Check for Photonic Integrated Circuit – Curvilinear Feature Extraction and Validation," Design Automation and Test in Europe (DATE) 2015, Grenoble, France, 9-13 March 2015

F. Teysseyre, D. Navarro, I. O'Connor, F. Cascio, F. Cenni, O. Guillaume, "Fast optical simulation from a reduced set of impulse responses using SystemC AMS," Design Automation and Test in Europe (DATE) 2015, Grenoble, France, 9-13 March 2015

H. Li, S. Le Beux, Y. Thonnart, I. O'Connor, "Complementary Communication Path for Energy Efficient on-chip Optical Interconnects," ACM Design Automation Conference (DAC), San Francisco (CA), USA, 7-11 June 2015

Q. An, L. Su, J. O. Klein, S. Le Beux, I. O'Connor, W. Zhao, "Full-adder circuit design based on all-spin logic device," IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 163-168, Boston (MA), USA, 8-10 July 2015

R. Cao, J. Ferguson, A. Bakker, T. Korthorst, A. Arriordaz, I. O'Connor, "Photonic designs with EDA approach: A novel methodology for curve design validation," IEEE Photonics Summer Topicals Meeting Series (SUM), pp. 29-30, Nassau, Bahamas, 13-15 July 2015

J. Sepulveda, S. Le Beux, J. Luo, C. Killian, D. Chillet, H. Li, I. O Connor, O. Sentieys, "Communication Aware Design Method for Optical Network-on-Chip," IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp. 243-250, Turin, Italy, 23-25 September 2015

H. Li, A. Fourmigue, S. Le Beux, I. O'Connor, G. Nicolescu, "A Thermal-Aware Laser Tuning Approach for Silicon Photonic Interconnects," 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), Dresden, Germany, 18 March 2016

O. Sentieys, J. Sepulveda, S. Le Beux, J. Luo, C. Killian, D. Chillet, I. O'Connor, H. Li, "Design Space Exploration of Optical Interfaces for Silicon Photonic Interconnects," 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), Dresden, Germany, 18 March 2016

R. Cao, J. Ferguson, C. Cone, A. Arriordaz, I. O’Connor, "Enabling Silicon Photonics Technology with EDA," 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), Dresden, Germany, 18 March 2016

J. Luo, C. Killian, D. Chillet, S. Le Beux, I. O'Connor, O. Sentieys, "Wavelength Allocation for Efficient Communications on Optical Network-on-Chip," ECSI Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.1656-1658, Rennes, France, 12-14 October 2016

C. Killian, D. Chillet, S. Le Beux, O. Sentieys, V.D. Pham, I. O'Connor, "Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques," IEEE/ACM Design Automation Conference (DAC), Austin (TX), USA, 18-22 June 2017

Q. An, S. Le Beux, I. O'Connor, J.O. Klein, W. Zhao, “Arithmetic Logic Unit based on all-spin logic devices,” IEEE International New Circuits and Systems Conference (NEWCAS), pp. 317-320, Strasbourg, France, 25-28 June 2017 

K. Cheng, S. Le Beux, I. O'Connor, "Hybrid Topologies for Reconfigurable Matrices Based on Nano-Grain Cells," IEEE International Conference on Rebooting Computing (ICRC), Washington (DC), USA, 8th-9th November 2017

Z. Li, C. Monat, S. Le Beux, X. Letartre, I. O'Connor, "An Energy-Efficient Reconfigurable Nanophotonic Computing Architecture Design: Optical Lookup Table," IEEE International Conference on Rebooting Computing (ICRC), Washington (DC), USA, 8th-9th November 2017

Q. An, S. Le Beux, I. O'Connor, J.O. Klein, "Large scale, high density integration of all spin logic," Design, Automation and Test in Europe (DATE), Dresden, Germany, 19-23 March 2018 (DOI: 10.23919/DATE.2018.8341992)

A. Perodou, A. Korniienko, G. Scorletti, I. O'Connor, "Design Method of Passive Ladder Filters using a Generalized Variable: a First Step," IEEE Conference on Design of Circuits and Integrated Systems, Lyon, France, 14-16 November 2018

S. Rigault, N. Moeneclaey, L. Labrak, Ian O’Connor, "CMOS VCSEL driver dedicated for sub-nanosecond laser pulses generation in SPAD-based time-of-flight rangefinder", IEEE Conference on Design of Circuits and Integrated Systems, Lyon, France, 14-16 November 2018 (DOI: 10.1109/DCIS.2018.8681460)

S. Rigault, N. Moeneclaey, L. Labrak, Ian O’Connor, "A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications", IEEE International System-on-Chip Conference (SOCC), Singapore, 3-6 September 2019 (DOI: 10.1109/SOCC46988.2019.1570548090)

A. Brik, L. Labrak, L. Carrel, I. O'Connor, R. Iskander, "Fast extraction of predictive models for integrated circuits using n-performances Pareto fronts", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Cuzco, Peru, 6-9 October 2019 (DOI: 10.1109/VLSI-SoC.2019.8920305)

E. Dupuis, D. Novo, I. O'Connor, A. Bosio, "On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression", Design, Automation and Test in Europe (DATE), Grenoble, France, 9-13 March 2020 (DOI: 10.23919/DATE48585.2020.9116350)

A. Bosio, I. O’Connor, G.S. Rodrigues, F.K. Lima, S. Hamdioui, "Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms," Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Marrakech, Morocco, 1-3 April 2020 (DOI: 10.1109/DTIS48698.2020.9081268)

E. Dupuis, D. Novo, I. O’Connor, A. Bosio, "Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing," Int. Symp. Design and Diagnostics of Electronic Circuits & Systems (DDECS), Novi Sad, Serbia, 22-24 April 2020 (DOI: 10.1109/DDECS50862.2020.9095658)

A. Brik, L. Labrak, I. O'Connor, D. Saias, "Fast hierarchical system synthesis based on predictive models," IEEE International New Circuits and Systems Conference (NEWCAS), Montreal (QC), Canada, 16-19 June 2020 (DOI: 10.1109/NEWCAS49341.2020.9159765)

A. Poittevin, C. Mukherjee, I. O'Connor, C. Maneux, G. Larrieu, A. Kumar, F. Marc, A. Lecestre, M. Deng, S. Le Beux, "3D logic cells design and results based on Vertical NWFET technology including tied compact model," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Salt Lake City (UT), USA [virtual], 5-9 October 2020 (DOI: 10.1109/VLSI-SOC46417.2020.9344094)

E. Dupuis, D. Novo, I. O'Connor, A. Bosio, "Fast exploration of weight sharing opportunities for CNN compression" DATE 2021 Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021), Grenoble (virtual), France, 5th February 2021

O. Sentieys, S. Filip, D. Briand, D. Novo, E. Dupuis, I. O’Connor, A. Bosio, "AdequateDL: Approximating Deep Learning Accelerators," International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), p. 37-40, Vienna, Austria, 7-9 April 2021 (DOI: 10.1109/DDECS52668.2021.9417026)

A. Bosio, I. O’Connor, M. Traiola, J. Echavarria, J. Teich, M.A. Hanif, M. Shafique, S. Hamdioui, B. Deveautour, P. Girard, A. Virazel, K. Bertels, "Emerging Computing Devices: Challenges and Opportunities for Test and Reliability," 26th IEEE European Test Symposium (ETS), virtual, 24-28 May 2021 (DOI: 10.1109/ETS50041.202 1.9465409)

F. Pavanello, I. O’Connor, U. Rührmair, A.C. Foster, D. Syvridis, "Recent Advances in Photonic Physical Unclonable Functions," 26th IEEE European Test Symposium (ETS), virtual, 24-28 May 2021 (DOI: 10.1109/ETS50041.2021.9465434)

C. Zrounba, S. Cueff, S. Le Beux, I. O’Connor, F. Pavanello, "Exploration of the optical behavior of phase-change materials integrated in silicon photonics platforms," Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC), virtual, 21-25 June 2021 (DOI: 10.1109/CLEO/Europe-EQEC52157.2021.9542745)

C. Marchand, I. O’Connor, M. Cantan, E.T. Breyer, S. Slesazeck, T. Mikolajick, "FeFET based Logic-in-Memory: an overview," 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Apulia, Italy, 28-30 June 2021, (DOI: 10.1109/DTIS53253.2021.9505078)

I. O’Connor, A. Poittevin, S. Le Beux, A. Bosio, Z. Stanojevic, O. Baumgartner, C. Mukherjee, C. Maneux, J. Trommer, T. Mikolajick, G. Larrieu, "Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology," 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), Caen, France, 1-3 September 2021, (DOI: 10.1109/EuroSOI-ULIS53016.2021.9560180)

M. Traiola, J. Echavarria, A. Bosio, J. Teich, I. O'Connor, "Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits," IEEE/ACM International Conference On Computer-Aided Design (ICCAD), Munich (virtual), Germany, 1-5 November 2021 (DOI: 10.1109/ICCAD51958.2021.9643561)

C. Maneux, C. Mukherjee, M. Deng, M. Dubourg, L. Reveil, G. Bordea, A. Lecestre, G. Larrieu, J. Trommer, E.T. Breyer, S. Slesazeck, T. Mikolajick, O. Baumgartner, M. Karner, D. Pirker, Z. Stanojevic, David A. Atienza, A. Levisse, G. Ansaloni, A. Poittevin, A. Bosio, D. Deleruyelle, C. Marchand, I. O'Connor, "Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence," IEEE International Electron Device Meeting (IEDM), San Francisco (CA), USA, 11-15 December 2021

E. Dupuis, D. Novo, I. O'Connor, A. Bosio, "A Heuristic Exploration to Retraining-free Weight Sharing for CNN Compression," ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 134 – 139, Taipei, Taiwan (virtual), 17-20 January 2022

C. Bolchini, A. Bosio, L. Cassano, B. Deveautour, G. Di Natale, A. Miele, I. O'Connor, I. Vatajelu, "Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?" IEEE Int. Symp. Design and Diagnostics of Electronic Circuits and Systems (DDECS), Prague, Czech Republic, 6-8 April 2022

M. Barbareschi, A. Bosio, I. O’Connor, P. Fišer, M. Traiola, "A Design Space Exploration Framework for Memristor-Based Crossbar Architecture," IEEE Int. Symp. Design and Diagnostics of Electronic Circuits and Systems (DDECS), Prague, Czech Republic, 6-8 April 2022

M. Abdalla, C. Zrounba, R. Cardoso, G. Ren, A. Boes, A. Mitchell, A. Bosio, I. O’Connor, F. Pavanello, "Photonic time-delay reservoir computing based on an asymmetric Mach-Zehnder interferometer with reconfigurable memory capacity," 23rd European Conference on Integrated Optics (ECIO), Milan, Italy, 4-6 May 2022

A. Piri, S. Sepide, M. Barbareschi, B. Deveautour, S. Di Carlo, I. O'Connor, A. Savino, M. Traiola, A. Bosio, "Input-Aware Approximate Computing," IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), Cluj-Napoca, Romania, 19-21 May, 2022

A. Poittevin, C. Marchand, A. Bosio, I. O'Connor, C. Maneux, C. Mukherjee, "Comprehensive Logic Cell Design Methodology Specific to VNWFET," IEEE Int. New Circuits and Systems Conference (NEWCAS), Quebec City (QC), Canada, 19-22 June 2022

R. Cardoso, L. Arif, C. Zrounba, F. Pavanello, I. O'Connor, L. Virot, S. Le Beux, "Energy Efficient on-Chip Optical Broadcast with partial-Absorption Photodiodes," IEEE Int. New Circuits and Systems Conference (NEWCAS), Quebec City (QC), Canada, 19-22 June 2022

P.A. Matrangolo, C. Marchand, I. O'Connor, D. Navarro, "Hardware Emulation of FeFET on FPGA," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pafos, Cyprus, 4-6 July 2022

A. Bosio, B. Deveautour, I. O'Connor, "Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pafos, Cyprus, 4-6 July 2022 (DOI: 10.1109/ISVLSI54635.2022.00070)

C. Maneux, C. Mukherjee, M. Deng, B. Neckel Wesling, L. Réveil, Z. Stanojevic, O. Baumgartner, I. O’Connor, A. Poittevin, G. Larrieu, "Circuit Design Flow dedicated to 3D vertical nanowire FET," IEEE Latin American Electron Devices Conference (LAEDC), Puebla, Mexico, 4-6 July 2022 (DOI: 10.1109/LAEDC54796.2022.9908233)

C. Zrounba, R. Cardoso, M. Abdalla, S. Cueff, A. Bosio, S. Le Beux, X. Letartre, I. O'Connor, F. Pavanello, "Comparing Rib and Slot Waveguides for Phase-Change Material Devices in SOI Platforms," Advanced Photonics Congress, Maastricht, Netherlands, 25-28 July 2022

L. Réveil, C. Mukherjee, C. Maneux, M. Deng, F. Marc, A. Kumar, G. Larrieu, A. Poittevin, I. O'Connor, O. Baumgartner, D. Pirker, "Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors," 30th IFIP/IEEE International Conference on Very Large-Scale Integration (VLSI-SoC 2022), Patras, Greece, 3-5 October 2022

R. Cardoso, C. Zrounba, M. Abdalla, P. Jimenez, M. Gomes, B. Charbonnier, F. Pavanello, I. O'Connor, S. Le Beux, "Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials," Design, Automation and Test in Europe (DATE), Antwerp, Belgium, 17-19 April 2023

T. Shahroodi, R. Cardoso, M. Zahedi, S. Wong, A. Bosio, I. O'Connor, S. Hamdioui, "Lightspeed binary neural networks using optical phase-change materials," Design, Automation and Test in Europe (DATE), Antwerp, Belgium, 17-19 April 2023

S. Pappalardo, A. Ruospo, I. O'Connor, B. Deveautour, E. Sanchez, A. Bosio, "A Fault Injection Framework for AI Hardware Accelerators," IEEE Latin-American Test Symposium (LATS), Veracruz, Mexico, 21-24 March 2023

S. Pappalardo, A. Ruospo, I. O’Connor, B. Deveautour, E. Sanchez, A. Bosio, "Resilence-Performance Tradeoff Analisys of Deep Neural Network Accelerator," 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Tallinn, Estonia, 3-5 May 2023

R. Cardoso, C. Zrounba, M. Abdalla, P. Jimenez, M. Gomes, B. Charbonnier, F. Pavanello, I. O'Connor, S. Le Beux, "Photonic Convolution Engine Based on Phase-Change Materials and Stochastic Computing," in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Foz do Iguacu, Brazil, 20-23 June 2023, (DOI: 10.1109/ISVLSI59464.2023.10238608)

A. Piri, S. Pappalardo, S. Barone, M. Barbareschi, B. Deveautour, M. Traiola, I. O'Connor, A. Bosio, "Input-aware accuracy characterization for approximate circuits," 8th Workshop on Approximate Computing (AxC), Porto, Portugal, 27 June 2023

Y. Wang, C. Mukherjee. H. Rezgui, M. Deng, C. Maneux, S. Mannaa, I. O’Connor, J. Müller, S. Pelloquin, G. Larrieu, "Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design," 53rd IEEE European Solid-State Device Research Conference (ESSDERC), pp. 57-60, Lisbon, Portugal, 2023 (DOI: 10.1109/ESSDERC59256.2023.10268560)

C. Zrounba, R. Cardoso, M. Gomes de Queiroz, P. Jimenez, M. Abdalla, A. Bosio, S. Le Beux, F. Pavanello, I. O’Connor, "Introducing SPECS: Scalable Photonic Event-driven Circuit Simulator," 49th European Conference on Optical Communications (ECOC), Glasgow, Scotland, 1-5 October 2023

S. Pappalardo, A. Piri, A. Ruospo, I. O'Connor, B. Deveautour, A. Bosio, E. Sanchez, "Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator," 36th IEEE Int. Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Juan-Les-Pins, France, 3-5 October 2023

M. Gomes de Queiroz, R. Cardoso, M. Abdalla, P. Jimenez, I. O’Connor, A. Bosio, F. Pavanello, "Power Reduction in Photonic Meshes by MZI Optimization," Frontiers in Optics + Laser Science (FiO+LS), Seattle (WA), USA, 9-12 October 2023

S. Pappalardo, A. Piri, A. Ruospo, I. O'Connor, B. Deveautour, E. Sanchez, A. Bosio, "Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator," IEEE Workshop on Automotive Reliability, Test and Safety (ARTS), Anaheim (CA), United States, 12-13 October 2023

M. Abdalla, M. Gomes, P. Jimenez, R. Cardoso, C. Zrounba, G. Ren, A. Boes, A. Mitchell, A. Bosio, I. O’Connor, Fabio Pavanello, "Exploring the bandwidth-limited readout in coherent photonic reservoir computing," Int. Conf. Neuromorphic, Natural and Physical Computing (NNPC), Hanover, Germany, 25-27 October 2023

R. Cardoso, C. Zrounba, M. Abdalla, P. Jimenez, M. Gomes, B. Charbonnier, F. Pavanello, I. O'Connor, S. Le Beux, "Signed Convolution in Photonics with Phase-Change Materials using Mixed-Polarity Bitstreams," 29th Asia and South Pacific Design Automation Conference (ASP-DAC), Incheon, South Korea, 22-25 January 2024

T. Shahroodi, R. Cardoso, S. Wong, A. Bosio, I. O'Connor, S. Hamdioui, "High-Performance Data Mapping for BNNs on PCM-based Integrated Photonics," IEEE/ACM Design, Automation and Test in Europe (DATE), Valencia, Spain, 25-27 March 2024

I. O'Connor, S. Mannaa, A. Bosio, B. Deveautour, D. Deleruyelle, T. Obukhova, C. Marchand, Jens T., C. Cakirlar, B. Neckel Wesling, T. Mikolajick, O. Baumgartner, M. Thesberg, D. Pirker, C. Lenz, Z. Stanojevic, M. Karner, G. Larrieu, S. Pelloquin, K. Moustakas, J. Muller, G. Ansaloni, A. Amirshahi, D. Atienza, J.L. Rouas, L. Ben Letaifa, G. Bordea, C. Brazier, Y. Wang, C. Mukherjee, M. Deng, M. François, H. Rezgui, L. Reveil, C. Maneux, "The 3D Neural Network Compute Cube (N2C2) Concept enabling Efficient Hardware Transformer Architectures towards Speech-to-Speech Translation," IEEE/ACM Design, Automation and Test in Europe (DATE), Valencia, Spain, 25-27 March 2024