Laboratory (COA)

17.01.2020:

• Realize each of the following problems using Gate-Level Modelling

1. A full subtractor has three 1-bit inputs and two 1-bit outputs D (difference) and B(borrow). Draw the truth table of the full subtractor. Implement the circuit using Verilog hardware language.

2. Write down the truth table of overflow detector circuit which is taught in the theory class. Realize it using Verilog hardware description language.

3. Design a 2-4 decoder using Verilog language.

24.01.2020:

• Realize each of the following problems using Gate-Level Modelling

1. Design 4-bit Full Adder by cascading four 1-bit full adders.

2. Implement 4-bit Carry Look-ahead Adder (CLA).

3. Implement 16-bit adder by cascading four 4-bit CLA.

4. Implement 8-1 MUX using Verilog language.

31.01.2020:

07.02.2020

• Implement SR latch.
• Implement SR Flip-flop.
• 
  

14.02.2002:

• Write down the truth table of JK flip flop. Implement the circuit using Verilog.
• Convert SR flip flop to D flip flop. Implement the circuit using Verilog.
• Convert JK flip flop to D flip flop. Implement the circuit using Verilog.
• Convert T flip flop to JK flip flop. Implement the circuit using Verilog.