Energy-Efficient Circuits & Systems Laboratory

Publications List

[Journal Papers]

    1. P. Pal, K.-J. Lee, S. Thunder, S. De, P.-T. Huang, and Y.-H. Wang, “Bending Resistant Multi-bit Memristor for Flexible Precision Inference Engine Application,” IEEE Transactions on Electron Devices, Vol. 69, No. 8, Aug., 2022.

    2. A. S. Bora, T. H. Singh and P.-T. Huang, “Digi-FH-OFDM: An All-Digital Wideband Frequency-hopped OFDM System,” Physical Communication (PHYCOM), Vol. 52, June, 2022.

    3. W. Lu, P.-T. Huang, H.-M. Chen and W. Hwang, “An Energy-Efficient 3D Cross-Ring Accelerator with 3D-SRAM Cubes for Hybrid Deep Neural Networks ,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 11, No. 4, pp.776-788, Dec. 2021.

    4. Y.-W. Liu, H.-W. Hu, S.-J. Chang, K.-N. Chen, P-.Y. Hsieh, H.-T. Chung, J.-H. Liu, P.-T. Huang, C.-C. Yang, C.-H. Shen, J.-M. Shieh and C. Hu, “Single-crystal islands (SCI) for monolithic 3D and back-end-of-line FinFET circuits,” IEEE Transactions on Electron Devices, Vol. 68, No. 10, pp. 5257-5262, Oct. 2021.

    5. L.-S. Shen, T.-W. Chang, K.-T. Feng and P.-T. Huang, “Design and Implementation for Deep Learning based Adjustable Beamforming Training for Millimeter Wave Communication Systems,” IEEE Transactions on Vehicular Technology (TVT), vol. 70, no. 3, pp. 2413-2427, March 2021.

    6. T. H. Singh, S. B. Jigalur, and P.-T. Huang, “Rotational Motion-Aware Beam Refinement for High-Throughput mmWave Communications,” Wireless Networks, Feb. 2021.

    7. P.-T. Huang, I.-C. Wu, C.-Y. Wu and W. Hwang, “Energy-Efficient Accelerator Design with Tile-based row-independent compressed Memory for Sparse Compressed Convolutional Neural Networks,” IEEE Open Journal of Circuits and Systems, vol. 2, pp. 131-143, 2021.

    8. K.-T. Feng, L.-H. Shen, C.-Y. Li, P.-T. Huang, S.-Hs. Wu, L.-C. Wang, Y.-B. Lin, and M.-C. F. Chang, "3D On-Demand Flying Mobile Communication for Millimeter Wave Heterogeneous Networks," IEEE Network, vol. 34, no. 5, pp. 198-204, Sept./Oct. 2020.

    9. S.-F. Cheng, P.-T. Huang, L.-C. Wang and M.-C. F. Chang, "Built-In Self-Test/Repair Methodology for Multiband RF-Interconnected TSV 3D Integration,” IEEE Design & Test, Vol. 36, No. 6, pp. 63-71, Dec. 2019.

    10. Y.-C. Huang, P.-T. Huang, S.-L. Wu, Y.-C. Hu, Y.-H. You, J.-M. Chen, Y.-Y. Huang, H.-C. Chang, Y.-H. Lin, J.-R. Duann, T.-W. Chiu, W. Hwang, K.-N. Chen, C.-T. Chuang and J.-C. Chiou, “An Ultra-High-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes,” IEEE Transactions on Biomedical Circuits and Systems, Vol. 11, No. 5, pp. 1013-1025, Oct. 2017. (Invited paper)

    11. S.-L. Wu, K.-Y. Li, P.-T. Huang, W. Hwang, M.-H. Tu, S.-C. Lung, W.-S. Peng, H.-S. Huang, K.-D. Lee, Y.-S. Kao and C.-T. Chuang, “A 0.5V 28nm 256kb Mini-Array Based 6T SRAM with Threshold Power-Gating, Low-Swing Global Read Bit-Line and Vtrip-Tracking Write-Assist,” IEEE Transactions on Circuits and Systems-I (TCAS-I), Vol. 64, No. 7, pp. 1791-1802, March, 2017.

    12. Y.-C. Hu, Y.-C. Huang, P.-T. Huang, S.-L. Wu, H.-C. Chang, Y.-T. Yang, Y.-H. You, J.-M. Chen, Y.-Y. Huang, Y.-H. Lin, J.-R. Duann,T.-W. Chiu, W. Hwang, C.-T. Chuang, J.-C. Chiou, and K.-N. Chen, "An Advanced 3D/2.5D Heterogeneous Integration Packaging for High Density Neural Sensing Microsystem," IEEE Transactions on Electron Devices, Vol. 64, No. 4, pp. 1666-1673, April, 2017.

    13. Y. Du, W.-H. Cho, P.-T. Huang, Y. Li, C.-H. Wong, J. Du, , Y. Kim, B. Hu, L. Du, S.-J. Lee and M.-C. F. Chang, “A 16 Gb/s 14.7 mW Tri-Band Cognitive Serial Link Transmitter with Forwarded Clock to Enable PAM-16 / 256-QAM and Channel Response Detection,” IEEE Journal of Solid-State Circuits, Vol. 52, No. 4, pp. 1111-1122, April 2017. (Invited paper)

    14. Y. Li, W.-H. Cho, Y. Du, J. Du, P.-T. Huang, S.-J. Lee, and M.-C. F. Chang, “Carrier Synchronization for Multiband RF Interconnect (MRFI) to Facilitate Chip-to-Chip Wireline Communication,” IET Electronics Letters, Vol. 52, N0. 7, pp.535-537, April 2016.

    15. C.-W. Chang, L.-C. Chou, P.-T. Huang, S.-L. Wu, S.-W. Lee, C.-T. Chuang, K.-N. Chen, , W. Hwang, K.-H. Chen, C.-T. Chiu, H.-M. Tong and J.-C. Chiou, “ A Double-Sided, Single-Chip Integration Scheme using Through-Silicon-Via for for Neural Sensing Applications,” Biomedical Microdevice, 17(1):1-15, Jan. 2015.

    16. P.-T. Huang, S.-L. Wu, Y.-C. Huang, L.-C. Chou, T.-C. Huang, T.-S. Wang, Y.-R. Lin, C.-A. Cheng, W.-W. Shen, C.-T. Chuang, K.-N. Chen, J.-C. Chiou, W. Hwang and H.-M. Tong, “2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications,” IEEE Transactions on Biomedical Circuits and Systems, Vol. 8, No. 6, pp.810-823, Dec. 2014. (Invited Paper)

    17. L.-C. Chou, C.-W. Chang, P.-T. Huang, J.-C. Chiou, C.-T. Chuang, W. Hwang, K.-N. Chen, C.-H. Wu, K.-H. Chen, C.-T. Chiu and H.-M. Tong, “A New Fabrication Process for TSV-based Bio-signal Packaging,” Storage Management Solutions, pp. 157-168, Issue 3, May 2014.

    18. L.-C. Chou, S.-W. Lee, P.-T. Huang, C.-W. Chang, C.-H. Chiang, S.-L. Wu, C.-T. Chuang, J.-C. Chiou, W. Hwang, C.-H. Wu, K.-H. Chen, C.-T. Chiu, H.-M. Tong and K.-N. Chen, “A TSV-Based Bio-Signal Package with u-Probe Array,” IEEE Electron device Letter, Vol. 35, No. 2, pp. 256-258, Feb. 2014.

    19. P.-T. Huang and W. Hwang, “Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Network,” Journal of Electrical and Computer Engineering, 19 Pages, Feb. 2012.

    20. P.-T. Huang and W. Hwang, “Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Network,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 11, pp.2412-2424, Nov. 2011.

    21. P.-T. Huang and W. Hwang, “A 0.047fJ/Bit/Search 65nm 256x144 Energy-Efficient TCAM Macro for Network Routers,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 2, pp.507-519, Feb. 2011.

    22. P.-T. Huang, X.-R. Lee, H.-C. Chang, C.-Y. Lee and W. Hwang, “A Low Power DCVSPG Pulsed Latch for Viterbi Decoder,” Journal of Low Power Electronics, Vol. 6, No. 4, pp. 551-562, Dec. 2010.

    23. P.-T. Huang, S.-W. Chang, W.-Y. Liu and W. Hwang, “Energy-Efficient Design for Ternary Content Addressable Memory,”International Journal of Electrical Engineering, Vol. 15, No.2, pp.97-108, 2008. (Invited Paper)

[Top Conference Papers]

    1. K.-Y. Hsiang, Y.-C. Chen , F.-S. Chang, C.-Y. Lin, C.-Y. Liao, Z.-F. Lou, J.-Y. Lee, W.-C. Ray, Z.-X. Li, C.-C. Wang, H.-C. Tseng, P.-H. Chen, J.-H. Tsai, M. H. Liao, T.-H. Hou, C. W. Liu, P.-T. Huang, P. Su, and M. H. Lee, “Novel Opposite Polarity Cycling Recovery (OPCR) of HfZrO2 Antiferroelectric-RAM with an Access Scheme Toward Unlimited Endurance”, IEEE International Electron Devices Meeting (IEDM), 2022

    2. J. Zhang, W. Lu, P.-T. Huang, S.-H. Li, T.-Y. Hung, S.-H. Wu, M.-J. Dai, I-S. Chung, W.-C. Chen, C.-H. Wang, S.-S. Sheu, H.-M Chen, K.-N. Chen, W.-C. Lo and C.-I Wu, " An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology," IEEE Symposium on VLSI circuits, 2022.

    3. H.-C. Chung, B-J. Shih, C.-C. Yang, N.-C. Lin, P.-T. Huang, Yun-Ping Lan, Kuan-Fu Lai, Wan-Ting Hsu,Yu-Ming Pan, Zhong-Jie Hong, Han-Wen Hu, Huang-Chung Cheng, C.-H. Shen, J.-M. Shieh, D.-C. Chang, W.-K. Yeh, C. Hu, and K.-N. Chen, "Ge Single-Crystal-Island (Ge-SCI) Technique for BEOL FinFET Switch Arrays in Monolithic 3D Fully Integrated Voltage Regulators," IEEE International Electron Devices Meeting (IEDM), Dec. 2021.

    4. P.-T. Huang, Y.-W. Liu, K.-F. Lai, Y.-P. Lan, T.-H. Tsai, B.-J. Shih, P.-Y. Hsieh, C.-C. Yang, C.-H. Shen, J.-M. Shieh, D.-Chiang Chang, K.-N. Chen, W.-K. Yeh, and C. Hu, “Crystal-Orientation-Tolerant Voltage Regulator using Monolithic 3D BEOL FinFETs in Single-Crystal Islands for On-Chip Power Delivery Network,” IEEE International Electron Devices Meeting (IEDM), pp. 40.6.1-40.6.4, Dec. 2020.

    5. C.-C. Yang, T.-Y. Hsieh, P.-H. Chen, T.-Y. Hsieh, P.-T. Huang, Y.-T. Lin, C.-H. Shen, J.-M. Shieh, D.-C. Chang, W.-K. Yeh, M.-C. Wu, and Y.-H. Lee, "Ultrahigh responsivity and tunable photogain BEOL compatible MoS2 phototransistor array for monolithic 3D image sensor with block-level sensing circuits," IEEE Symposium on VLSI Technology, 2020.

    6. P.-Y. Hsieh, Y.-J. Chang, P.-J. Chen, C.-L. Chen, C.-C. Yang, P.-T. Huang, Y.-J. Chen, C.-M. Shen, Y.-W. Liu, C.-C. Huang, M.-C. Tai, W.-C. Lo, C.-H. Shen, J.-M. Shieh, D.-C. Chang, K.-N. Chen, W.-K. Yeh, and C. Hu, “Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators,” IEEE International Electron Devices Meeting (IEDM), 2019.

    7. C.-C. Yang, T.-Y. Hsieh, P.-T. Huang, K.-N. Chen, W.-C. Wu, S.-W. Chen, C.-H. Chang, C.-H. Shen, J.-M. Shieh, C. Hu, M.-C. Wu, W.-K. Yeh, "Location-controlled-grain technique for monolithic 3D BEOL FinFET Circuits," IEEE International Electron Devices Meeting (IEDM), 2018.

    8. Y. Du, W.-H. Cho, Y. Li, C.-H. Wong, J. Du, P.-T. Huang, Z.-Z. Chen, S.-J. Lee, and M.-C. F. Chang, “A 16Gb/s 14.7mW Tri-Band Cognitive Transmitter with Forwarded-Clock to Enable PAM-16/256-QAM and Channel Response Detection in 28nm CMOS,” IEEE Symposium on VLSI circuits, pp. 172-173, 2016.

    9. Y.-C. Huang, Y.-C. Hu, P.-T. Huang, S.-L. Wu, Y.-H. You, J.-M. Chen, Y.-Y. Huang, H.-C. Chang, Y.-H. Lin, J.-R. Duann, T.-W. Chiu, W. Hwang, C.-T. Chuang, J.-C. Chiou and K.-N. Chen, “Integration of Neural Sensing Microsystem with TSV-embedded Dissolvable µ-Needles Array, Biocompatiable Flexible Interposer and Neural Recording Circuits,” IEEE Symposium on VLSI Technology, pp. 218-219, 2016.

    10. W.-H. Cho, Y. Li, Y. Du, C.-H. Wong, J. Du, P.-T. Huang, S.-J. Lee, H.-N. Chen, C.-P. Jou, F.-L. Hsueh and M.-C. F. Chang, “A 38mW 40Gb/s 4-Lane Tri-Band 4-PAM /16-QAM Transceiver in 28nm CMOS for High-Speed Memory Interface,” IEEE International Solid-State Circuits Conference (ISSCC), pp.184-185, 2016.

    11. P.-T. Huang, L.-C. Chou, T.-C. Huang, S.-L. Wu, T.-S. Wang, Y.-R. Lin, C.-A. Cheng, W.-W. Shen, K.-N. Chen, J.-C. Chiou, C.-T. Chuang, W. Hwang, K.-H. Chen, C.-T. Chiu, M.-H. Cheng, Y.-L. Lin and H.-M. Tong, “2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural Sensing Applications,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321, 2014.

    12. C.-W. Chang, P.-T. Huang, L.-C. Chou, S.-L. Wu, S.-W. Lee, C.-T. Chuang, K.-N. Chen, J.-C. Chiou, W. Hwang, Y.-C. Lee, C.-H. Wu, K.-H. Chen, C.-T. Chiu, and H.-M. Tong, “Through-Silicon-Via Based Double-Side Integrated Microsystem for Neural Sensing Applications,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 102-103, Feb. 17-21, 2013.

[Conference Papers]

    1. W. Lu, P.-Y. Ge, P.-T. Huang, H.-M. Chen and W. Hwang, “Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM,” IEEE International SoC Design Conference(ISoCC), 2022.

    2. J.-I Kao, W. Lu., P.-T. Huang and H.-M. Chen, “Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator,” IEEE International SoC Design Conference(ISoCC), 2022.

    3. S.-C. Wen and P.-T. Huang, "Design Exploration of An Energy-Efficient Acceleration System for CNNs on Low-Cost Resource-Constraint SoC-FPGAs," IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp.320-323, 2022.

    4. P.-T. Huang, T.-W. Liu, W. Lu, Y.-H. Lin, and W Hwang, “ An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks,” IEEE Inernational SoC Design Conference, 2021.

    5. S. Thunder, P. Pal, Y.-H. Wang and P.-T. Huang, “Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on α-IGZO Nanosheet and Bi-Layer Resistive Memory,” IEEE International Conference on IC Design and Technology, 2021.

    6. A. S. Bora, T. H. Singh and P.-T. Huang, “An All-Digital Wideband OFDM-Based Frequency-Hopping System Using RF Sampling Data Converters,” National Conference on Communications, pp.1-5, 2021.

    7. S.-Y. Ku, Y.-C. Tsai, T.-C. Chou, W.-H. Hu, Y.-R. Fang, Y.-J. Lin, P.-T. Huang, J.-C. Chiou, and K.-N. Chen, “dvanced 2.5D Heterogeneous Integrated Platform Using Flexible Biocompatible Substrate for Biomedical Sensing System,” IEEE Electronic Components and Technology Conference (ECTC), pp. 1020-1025, 2021.

    8. P. Pal, S. Thunder, M.-J. Tsai, P.-T. Huang, and Y.-H. Wang, “Benchmarking the Performance of Heterogeneous Stacked RRAM with CFET-SRAM and MRAM for Deep Neural Network Application Amidst Variation and Noise,” IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021.

    9. P.-T. Huang, T.-H. Tsai, P.-J. Yang, W. Hwang and H.-M. Chen, “Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs,” IEEE International System-on-Chip Conference (SOCC), pp. 248-253, 2020.

    10. C.-Y. Lo, P.-T. Huang, and W. Hwang, "Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs," IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp.320-323, 2020.

    11. J. D, C.-H. Wong, Y.-T. Tu, W.-H. Cho, Y. Li, Y. Du, P.-T. Huang, S.-J. Lee, and M.-C. F. Chang, "A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET," IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 16:1-16:8, 2019.

    12. H.-J. Tseng, P.-T. Huang, S.-L. Wu, S.-C. Lung, W.-C. Wang, W. Hwang and C.-T. Chuang, "28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications," IEEE International SOC Conference (SOCC), 2019.

    13. I.-C. Wu, P.-T. Huang, C.-Y. Lo and W. Hwang, "An Energy-Efficient Accelerator with Relative-Indexing Memory for Sparse Compressed Convolutional Neural Network," IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2019.

    14. H.-P. Lu, P.-T. Huang, K.-N. Chen, J.-C. Chiao and W. Hwang, "Fully-Integrated Neural Signal Amplifier using Switched-Capacitor Technique for Direct Current Rebuffing,” 2019 Symposium on Engineering, Medicine, and Biology Applications (SEMBA), 2019.

    15. Y.-S. Chan, P.-T. Huang, S.-L. Wu, S.-C. Lung, W.-C. Wang, W. Hwang and Ch.-T. Chuang, "0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process," IEEE International SOC Conference (SOCC), 2018.

    16. J. Cong, L. Guo, P.-T. Huang, P. Wei and T. Yu, "SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing," IEEE International Conference on Field-Programmable Logic and Applications , 2018.

    17. Y.-C. Wu, P.-T. Huang, S.-L. Wu, S.-C. Lung, W.-C. Wang, W. Hwang. and C.-T, Chuang, “28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications,” IEEE Symposium on VLSI Design, Automation and Test, pp. 1-4, 2018.

    18. J. Cong, L. Guo, P.-T. Huang, P. Wei and T. Yu, “SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing,” IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 206-206, 2018.

    19. P.-T. Huang, Y.-C. Huang, S.-L. Wu, Y.-C. Hu, M.-W. Lu, T.W. Sheng, F.K. Chang, C.-P. Lin, N.-S. Chang, H.-L. Chne, C.-S. Chen, T.-W. Chiu, W. Hwang, K.-N. Chen, C.-T. Chuang and J.-C. Chiou, “Wireless Neural-Sensing Microsystem using TSV-Embedded Dissolvable μ-Needle Array and Flexible Interposer,” 2018 Symposium on Engineering, Medicine, and Biology Applications (SEMBA), 2018.

    20. Y.-C. Huang, P.-T. Huang, S.-L. Wu, Y.-C. Hu, Y.-H. You, J.-M. Chen, Y.-Y. Huang, H.-C. Chang, Y.-H. Lin, J.-R. Duann, T.-W. Chiu, W. Hwang, K.-N. Chen, C.-T. Chuang, and J.-C. Chiou, "A 64-Channel Wireless Neural Sensing Microsystem with TSV-embedded Μicro-probe Array for Neural Signal Acquisition," TRANSDUCERS 2017 - 2017 International Solid-State Sensors, Actuators and Microsystems Conference, 2017.

    21. P.-T. Huang, Y.-C. Huang, S.-L. Wu, Y.-C. Hu, M.-W. Lu, T.W. Sheng, F.K. Chang, C.-P. Lin, N.-S. Chang, H.-L. Chne, C.-S. Chen, J.-R. Duann, T.-W. Chiu, W. Hwang, K.-N. Chen, C.-T. Chuang and J.-C. Chiou, “An Implantable 128-Channel Wireless Neural-Sensing Microsystem using TSV-Embedded Dissolvable μ-Needle Array and Flexible Interposer,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1160-1163, 2017.

    22. C.-N. Chang, Y.-N. Chen, P.-T. Huang, P. Su and C.-T. Chuang, "Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementation," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2849-2852, 2017.

    23. J.-M. Chen, P.-T. Huang, S.-L. Wu, C.-T. Chuang and W. Hwang, “Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Applications,” IEEE International SOC Conference (SOCC), pp. 18-23, 2016.

    24. P.-T. Huang, C. Y. Hao, Y-T. Chen, C.-L. Kuo, M.-C. F Chang and Jason Cong, “The SMEM Seeding Acceleration for DNA Sequence Alignment,” IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.32-39, 2016.

    25. Y.-C. Huang, P.-T. Huang, S.-L. Wu, Y.-C. Hu, Y.-H. You, J.-M. Chen, Y.-Y. Huang, H.-C. Chang, Y.-H. Lin, J.-R. Duann, T.-W. Chiu, W. Hwang, K.-N. Chen, C.-T. Chuang and J.-C. Chiou, “An Ultra-High-Density 256-Channel/25mm2 Neural Sensing Microsystem Using TSV-Embedded Neural Probes,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1302-1305, 2016.

    26. W.-S. Hsu, P.-T. Huang, S.-L. Wu, C.-T. Chuang, W. Hwang, M.-H. Tu, and M.-Y. Yin, “28nm Ultra-Low Power Near-/Sub-threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms,” IEEE Symposium on VLSI Design, Automation and Test, pp. 1-4, 2016.

    27. W.-H. Cho, Y. Li, Y. Kim, P.-T. Huang, Y. Du, S.-J. Lee, M.-C. Frank Chang, “A 5.4-mW 4-Gb/s 5-Band QPSK Transceiver for Frequency-Division Multiplexing Memory Interface,” IEEE Custom Integrated Circuits Conference (CICC), PP. 1-4, Sept. 2015.

    28. C.-Y. Huang, P.-T. Huang, C.-C. Yang, C.-T. Chuang and W. Hwang, “Energy-Efficient Gas Recognition System with Event-Driven Power Control,” IEEE International SOC Conference (SOCC), pp. 245-250, 2015.

    29. Y.-P. Kuo, P.-T. Huang, C.-S. Wu, C.-T. Chuang, Y.-H. Chu and W. Hwang, “All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration for Ripple Reduction,” IEEE International Symposium on VLSI Design, Automation and Test, pp. 1-4, April 2015.

    30. C.-C. Yang, P.-T. Huang, C.-Y. Huang, C.-T. Chuang and W. Hwang, “Low Power Algorithm-Architecture Co-Design of Fast Independent Component Analysis (FICA) for Multi-Gas Sensor Applications,” IEEE International Symposium on VLSI Design, Automation and Test, pp. 1-4, April 2015.

    31. P.-T. Huang, S.-L. Lai, C.-T. Chuang, W. Hwang, J. Huang, A. Hu, P. Kan, M Jia, K. Lv and B. Zhang, “0.339fJ/bit/search Energy-Efficient TCAM Macro Design in 40nm LP CMOS,” IEEE Asia Solid-State Circuits Conference (ASSCC), pp. 129-132, 2014.

    32. C.-Y. Chang, P.-T. Huang, Y.-C. Chen, T.-S. Chang and W. Hwang, “Thermal-Aware Memory Management Unit of 3D-Stacked DRAM for 3D High Definition (HD) Video,” IEEE International SOC Conference (SOCC), pp. 76-81, 2014.

    33. P.-T. Huang, Y.-L. Lin, C.-T. Chuang and W. Hwang, “μ-SPI: An On-Interposer Bus for 2.5D Heterogeneously Integrated Bio-Sensing Microsystems,” 25th VLSI Design /CAD Symposium, Aug. 2014.

    34. T.-H. Wang, P.-T. Huang, K.-N. Chen, J.-C. Chiou, K.-H. Chen, C.-T. Chiu, H.-M. Tong, C.-T. Chuang and W. Hwang, “Configurable Discrete Wavelet Transform (DWT) for Multi-Channel Neural Sensing Applications,” IEEE International Symposium on Circuits and Systems (ISCAS), pp.1841-1844, 2014.

    35. L.-C. Chou, S.-W. Lee, P.-T. Huang, C.-W. Chang, S.-L. Wu, C.-T. Chuang, J.-C. Chiou, W. Hwang, C.-H. Wu, K.-H. Chen, C.-T. Chiu, H.-M. Tong and Kuan-Neng Chen, “Integrated Microprobe Array and CMOS MEMS by TSV Technology for Bio-Signal Recording Application,” IEEE Electronic Components and Technology Conference (ECTC), pp.512-517, 2014.

    36. S.-L. Wu, P.-T. Huang, T.-C. Huang, K.-N. Chen, J.-C. Chiou, K.-H. Chen, C.-T. Chiu, H.-M. Tong, C.-T. Chuang and W. Hwang, “Energy-Efficient Low-Noise 16-Channel Analog- Front-End Circuit for Bio-potential Acquisition,” IEEE International Symposium on VLSI Design, Automation and Test, pp.117-120, 2014.

    37. L.-C. Chou, S.-W. Lee, Chuan-An Cheng, P.-T. Huang, C.-W. Chang, C.-H. Chiang, S.-L. Wu, C.-T. Chuang, J.-C. Chiou, W. Hwang, C.-H. Wu, K.-H. Chen, C.-T. Chiu, H.-M. Tong and K.-N. Chen, “A TSV-Based Heterogeneous Integrated Neural-Signal Recording Device with Microprobe Array,” IEEE VLSI-TSA Symposium, pp. 149-150, 2014.

    38. T.-C. Huang, P.-T. Huang, S.-L. Wu,K.-N. Chen, J.-C. Chiou, K.-H. Chen, C.-T. Chiu, H.-M. Tong, C.-T. Chuang and W. Hwang, “Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications,” IEEE Biomedical Circuits and Systems (BioCAS), pp. 238-241, 2013.

    39. T.-T. Chaing, P.-T. Huang, C.-T. Chuang, J-C Chiou, K.-N. Chen, K.-H. Chen, C.-T. Chiu, H.-M. Tong,and W. Hwang, “On-Chip Process-Temperature Senosr with Self-Compensation for TSV 3D Integration,” IEEE International SoC Conference, (SOCC), pp.370-375, Sept. 2012.

    40. P-T. Huang, T.-T. Chiang, H. Chiueh, C.-T. Chuang, J-C Chiou, K.-N. Chen, K.-H. Chen, C.-T. Chiu, H.-M. Tong, and W. Hwang, “Thermal Management with In-Situ Process-Temperature Sensor for TSV 3D-ICs,” 23th VLSI Design /CAD Symposium, Aug. 2012.

    41. P-T Huang, Yung Chang, Shiang-Fei Wang and Wei Hwang, “An Efficient Network Interface for Memory-Centric On-Chip Interconnection Network.” 23th VLSI Design /CAD Symposium, Aug. 2012.

    42. P.-J Yang, P.-T. Huang, Y. Chang and W. Hwang, “Substrate Noise Suppression Technique for Power Integrity of TSV 3D Integration,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3274-3277, 2012.

    43. W.-H. Du, P.-T. Huang, M.-H. Chang, and Wei Hwang, “A 2kb Built-In Row-Controlled Dynamic Voltage Scaling Near-/Sub-Threshold FIFO memory for WBANs,” IEEE International Symposium on VLSI Design, Automation and Test, pp. 1-4, 2012. (Best Paper Award Nomination).

    44. P.-T. Huang, T.-T. Chaing, H.-M. Chiueh and W. Hwang, “Thermal Control Mechanism with In-Situ Temperature Sensor for TSV 3D-ICs,” IEEE International Workshop on Thermal inverstigations of ICs and Systems (THERMINIC), pp. 189-194, Sept. 2011.

    45. P.-T. Huang, Y. Chang and W. Hwang, “On-Demand Memory Sub-System for Multi-Core SoCs,” IEEE International SoC Conference, (SOCC), pp. 122-127, Sept. 2011.

    46. T.-H. Lin, P.-T. Huang, and W. Hwang, “Power Noise Suppression Technique using Active Decoupling Capacitor for TSV 3D Integration,” IEEE International SoC Conference, (SOCC), pp. 209-212, Sept. 2010.

    47. P.-T. Huang and W. Hwang, “Energy-Efficient Techniques for Circuit Design in Netowork-on-Chip Platforms,” IEEE International Symposium on Green Circuits and Systems (ICGCS), pp. 305-310, Jun. 2010. (Invited Paper)

    48. P.-T. Huang and W. Hwang, “An adaptive Congestion-Aware Routing Algorithm for Mesh Network-on-Chip Platform,” IEEE International SoC Conference, (SOCC), pp. 375-378, Sept. 2009.

    49. Y. Chang, P.-T. Huang and W. Hwang, “A Capacitive Boosted Buffer for Energy-Efficient and Variation–Tolerant Sub-threshold Interconnect,” Electronic Technology Symposium (ETS), Jun. 2009. (Best Paper Award)

    50. M.-T. Chang, P.-T. Huang, and W. Hwang, “A Robust Ultra-low Power Asynchronous FIFO Memory with Self-Adaptive Power Control,” IEEE International SoC Conference, (SOCC), pp.175-178, Sept. 2008.

    51. P.-T. Huang, W.-L. Fang, and W. Hwang, “A Self-Calibrated Voltage Scaling Technique for Reliable Interconnections in Network-on-Chip,” 19th VLSI Design /CAD Symposium, Aug. 2008.

    52. L.-P. Chuang, M.-H. Chang, P.-T. Huang, C.-H. Kan, and W. Hwang, “A 5.2 mW All-Digital Fast-Lock Self-Calibrated Multiphase Delay-locked Loop,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3342-3345, May 2008.

    53. P.-T. Huang, S.-W. Chang, W.-Y. Liu, and W. Hwang, “Green Micro-architecture and Circuit Co-Design for Ternary Content Addressable Memory,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3322-3325, May 2008.

    54. P.-T. Huang, W.-L. Fang, Y.-L. Wang and W. Hwang, “Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip,” ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 77-83, Apr. 2008.

    55. M.-T. Chang, P.-T. Huang, and W. Hwang, “A 65nm Low Power 2T1D Embedded DRAM with Leakage Current Reduction,” IEEE International SOC Conference (SOCC), pp.207-210, Sept. 2007.

    56. W.-Y. Liu, P.-T. Huang and W. Hwang, “An Energy-Efficient 256x144 TCAM Design,” 18th VLSI/CAD Symposium, Aug. 2007. (Best Paper Award Nomination)

    57. P.-T. Huang, S.-W. Chang, W.-Y. Liu, and Wei Hwang, “A 256x128 Energy-Efficient TCAM with Novel Low Power Schemes,” IEEE International Symposium on VLSI Design, Automation and Test, pp.32-35, Apr. 2007.

    58. W.-L. Su, H.-M. Chieueh, P.-T. Huang and W. Hwang, “A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 553-556, Dec. 2006.

    59. P.-T. Huang, W.-K. Chang and W. Hwang, “Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1303-1307, Dec. 2006.

    60. J.-W. Yang, P.-T. Huang and W. Hwang, “On-chip DC-DD Converter with Frequency Detector for Dynamic Voltage Scaling Technology,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 667-671, Dec. 2006.

    61. W.-L. Su, P.-T. Huang, H.-M. Chiueh and W. Hwang, “A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder,” 17th VLSI Design/CAD Symposium, Aug. 2006.

    62. J.-W. Yang, P.-T. Huang and W. Hwang, “On-chip DC-DC Converter with Frequency Detector for Reconfigurable Multiplier-Accumulator Unit,” 17th VLSI/CAD Symposium, Aug. 2006.

    63. P.-T. Huang, W.-K. Chang and W. Hwang, “Low Power Content Addressable Memory with Pre-Comparison Scheme and Dual-Vdd Technique,” 17th VLSI/CAD Symposium, Aug. 2006.

    64. S.-W. Chang, P.-T. Huang and Wei Hwang, “A Novel Butterfly Match-line Scheme with Don’t Care Based Hierarchical Search-Line for TCAM,” 17th VLSI/CAD Symposium, Aug. 2006.

    65. P.-T. Huang and W. Hwang, “2-Level FIFO Architecture Design for Switch Fabrics in Network-on-Chip,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4863-4866, May 2006.

    66. C.-K. Tsai, P.-T. Huang and W. Hwang, “Low power Pulsed Edge-Triggered Latches Design,” 16th VLSI/CAD Symposium, Aug. 2005.

    67. S.-H. Lin, P.-T. Huang and W. Hwang, “A Power-Speed Optimization Technique of High-Speed Multiply-Accumulate Design,” 16th VLSI/CAD Symposium, Aug. 2005.

    68. P.-T. Huang and W. Hwang, “Low Power Encoding Schemes for Run-Time On-Chip Bus,” IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 1025-1028, Dec. 2004.