Link-Layer Desgin for 5G mmWave Communications (Smart Campus)

• Low-latency Video codec for interactive multimedia
• Motion-aware (sensor-aided) beamforming adaption scheme
• Application-driven low-latency MAC processor

Low-Power Embedded Memory Design

• Low-voltage memory circuits (Register, SRAM, FIFO, TCAM)
• PVT-tolerant R/W-assist techniques
• Low-power memory architecture

TSV 2.5D/3D Heterogeneously Integrated Neural-Sensing Microsystems

• Heterogeneous integration for neural-sensing microsstem
• Neural-signal acquistion and feature extraction circuits
• Area/power optimaiton for high-density neural-sensing

Fusion Data Management & Early Feedback for Multi-Sensor Fusion

• Dynamic data allocation with shared FIFO queues
• Event-driven sensor-fusion techniques
• Self-timed power control

Energy-Efficient Inter-Chip Communicaitons

• Multi-band signaling (RF-interconnect)
• Cognitive RF-I with channel learning
• System-level evaluation for TSV 3D integration

Accelerator-Rich Domain-Specific Computing

• BWT acceleration for DNA sequencing
• SMEM/SW heterogeneous acceleration system
• Load balance and resorce optimization