Energy-Efficient Circuits & Systems Laboratory
節能電路與系統實驗室
Energy-Efficient Circuits & Systems (EECS) group was established by Prof. Po-Tsang Huang. Our major goal is to explore pioneering low-power design techniques and methodologies of system integration for both power-limited and energy-limited applications. Our research spans across multiple levels of design abstraction from solid-state circuits, architectures, microsystems and software-hardware co-design technologies.
Recent Research Interests
[ MPSoC Architecture/Platform Design for IoT, AI & Communication Applications ]
Accelerator design for neural networks (CNN, RNN, LSTM, 3D-CNN...etc) using 3D-SRAM
Hierarchical configurable interconnect with 3D-SRAM for memory-centric computing
Memory sub-system for heterogeneous multi-core SoC/SiP
Accelerator-rich and memory-rich computer architectures for domain-specific computing
Energy-efficient FPGA-SoC platforms for mmWave radars & mmWave communications
System-level power analysis and noise reduction in High-performance computing (HPC) or 3DIC
[ Circuit/Technology Co-Design using Monolithic/TSV 3DIC, emerging memory & devices ]
SRAM-based and NVM-based computation-in-memory circuits and architecture for neural networks
Power management and data communications for 3D-IC (Monolithic 3D-IC & TSV 3D-IC)
Energy-Efficient digital IC (VLSI) design using emerging memory & devices
Low-power embedded memory design (Latch, SRAM, Register-File, FIFO, CAM/TCAM)
Ultra-low voltage IC design for IoT and biomedical applications
Biomedical circuits and microsystems for neural-sensing applications
Lab Award
"Monolithic 3D-IC Structure and Fabrication Using Location-Controlled-Grain Technique," 2019 Future Technology Award, MOST, Taiwan. (collaboration between NCTU and TSRI)
2021.03.09 Annual Party
2018.02.01 Semester-end party