RESEARCH

A 150 GHz amplifier in 65nm CMOS

• • Three-stage common-source stages with minimum matching losses

  • Dummy-prefilled microstrip lines for design-rule compliance

 A 600 GHz 30 dB gain, 2 mW Psat amplifier in InP-HBT process

• • Among the fastest amplifier reported with a record output power

  • 12-stage common-base for high-gain

  • Cross-coupled feedback stabilization

  • 4:1 differential-to-SE output combiner for high saturated output power

 A 300 GHz single-chip phase-locked loop (PLL) IC in InP-HBT process

• • Highest-frequency fundamental PLL reported.

  • 2:1 dynamic frequency divider for ultra-high frequency operation

  • Sub-harmonic phase detection to reduce circuit complexity

A 600 GHz single-chip transmitter (TX) chip in InP-HBT process

• • Highest-frequency RF front-end chip reported

  • Integrated sub-harmonic local oscillator (LO) PLL at 210 GHz

  • Sub-harmonic transmit mixer

Millimeterwave (60 GHz) sensor network experimental prototype

• • Simultaneous sensor localization and data read-out

  • 3D sensor localization using a narrow pencil beam and radar ranging techniques

  • Reflection-type sensor prototype using a slot antenna and PIN-diode modulator

Experimental prototype (60 GHz) for sensor network based on a distributed phased array

• • Local sensors collaborate to combine their RF carrier power to reach far-out reader.

  • Feedback-based approach to synchronize sensor phase/frequencies in distributed fashion.

Signal processing techniques for mismatch error correctons in time-interleaved ADCs (TIADC)

• • Time-interleaving enables much higher sampling frequencies than a single A-D converter

  • However, signal-to-noise ratios of TIADCs are significantly affected by mismatch errors

  • Various foreground/background signal processing techniques are developed to correct such mismatch errors