Bio

I am currently a Senior Manager and Research Scientist at NVIDIA in the Architecture Research Group, where I lead a team of researchers focusing on enabling technologies for high-bandwidth, energy-efficient future DRAM/NVRAM systems. Prior to joining NVIDIA, I was a Principal Researcher at AMD, where I concentrated on various aspects of future-generation heterogeneous GPGPU (“Fusion”) architectures. At AMD, I helped define the architecture of the High-Bandwidth Memory (HBM) stacked-memory standard and also contributed to the definition of the Heterogeneous System Architecture (HSA) standard. Before AMD, I was at NVIDIA on the product development side, where I was the lead architect for the memory system for several GPU families: GT200 and its derivatives GT218, GT216, and GT215 and the G80 derivatives (G84, G86, G92, G94, G96, and G98). I also led the architecture for the GPU memory system for the chipset-integrated parts MCP78 and MCP79.

Before getting into GPU research and development, I was at Texas Instruments, where I was part of a small 3-person team in Austin architecting the first superscalar ARM core (for use in TI's OMAP chips). For various business reasons, this architecture was transferred to ARM, where it was further developed and became the Cortex-A8. Before TI, I was at a network processor start-up in the Bay Area, Silicon Access Networks, which developed a chipset for high-performance routers. I was the chief processor architect, where I led the architecture of multi-threaded multi-core architecture with unique integrated ternary-CAM-keyed instruction dispatch. I also architected a longest-prefix match co-processor. Unfortunately, we were targeting a very high-end space, with only a few potential customers (the largest of which ended up using in-house designs).