Patents
Granted US Patents
11,789,649 Combined on-package and off-package memory system
11,709,812 Techniques for generating and processing hierarchical representations of sparse matrices
11,500,778 Prefetch kernels on data parallel processors
11,301,256 System and method for page-conscious GPU instruction
11,159,153 Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O
11,132,300 Memory hierarchy using page-based compression
10,713,059 Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units
10,657,094 Relaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses
10,599,606 424 encoding schemes to reduce coupling and power noise on PAM-4 data buses
10,585,801 Prefetch kernels on a graphics processing unit
10,522,193 Processor with host and slave operating modes stacked with memory
10,491,435 Unrelaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses
10,468,093 Systems and methods for dynamic random access memory (DRAM) sub-channels
10,079,044 Processor with host and slave operating modes stacked with memory
9,910,605 Page migration in a hybrid memory device
9,875,195 Data distribution among multiple managed memories
9,818,455 Query operations for stacked-die memory device
9,804,996 Computation memory operations in a logic layer of a stacked memory
9,766,936 Selecting a resource from a set of resources for performing an operation
9,734,059 Methods and apparatus for data cache way prediction based on classification as stack data
9,697,147 Stacked memory device with metadata management
9,690,350 Method and apparatus for power reduction during lane divergence
9,535,831 Page migration in a 3D stacked hybrid memory
9,489,321 Scheduling memory accesses using an efficient row burst value
9,477,605 Memory hierarchy using row-based compression
9,477,526 Cache utilization and eviction based on allocated priority tokens
9,454,419 Partitionable data bus
9,436,398 Memory interface supporting both ECC and per-byte data masking
9,406,403 Spare memory external to protected memory
9,367,455 Using predictions for store-to-load forwarding
9,354,892 Creating SIMD efficient code by transferring register state through common memory
9,317,296 High level software execution mask override
9,298,615 Methods and apparatus for soft-partitioning of a data cache for stack data
9,286,948 Query operations for stacked-die memory device
9,251,069 Mechanisms to bound the presence of cache blocks with specific properties in caches
9,244,629 Method and system for asymmetrical processing with managed data affinity
9,235,528 Write endurance management techniques in the logic layer of a stacked memory
9,229,803 Dirty cacheline duplication
9,218,204 A processing engine for complex atomic operations
9.183,055 Selecting a resource from a set of resources for performing an operation
9,135,185 Die-stacked memory device providing data translation
9,106,260 Parity data management for a memory architecture
9,075,730 Mechanisms to bound the presence of cache blocks with specific properties in caches
9,064,606 Memory interface supporting both ECC and per-byte data masking
9,021,207 Management of cache size
9,003,130 Multi-core processing device with invalidation cache tags and methods
8,949,544 Bypassing a cache when handling memory requests
8,935,472 Processing device with independently activatable working memory bank and methods
8,909,840 Data bus inversion coding
8,880,809 Memory controller with inter-core interference detection
8,726,139 Unified data masking, data poisoning, and data bus inversion signaling
8,510,518 Bandwidth-adaptive memory compression
8,330,766 Zero-bandwidth clears
8,217,813 System and method for low-latency data compression/decompression
7,870,350 Write buffer for read-write interlocks
7,868,901 Method and system for reducing memory bandwidth requirements in an anti-aliasing operation
7,047,317 High performance network address processor system
7,016,904 Method and system for rapid insertion of various data streams into sorted tree structures
6,988,189 Ternary content addressable memory based multi-dimensional multi-way branch selector and method of operating same
6,983,234 System and method for validating processor performance and functionality
6,961,843 Method frame storage using multiple memory circuits
6,950,923 Method frame storage using multiple memory circuits
6,725,308 Locking of computer resources
6,542,990 Array access boundary check by executing BNDCHK instruction with comparison specifiers
6,532,531 Method frame storage using multiple memory circuits
6,529,982 Locking of computer resources
6,430,649 Method and apparatus for enforcing memory reference dependencies through a load store unit
6,408,383 Array access boundary check by executing BNDCHK instruction with comparison specifiers
6,230,230 Elimination of traps and atomics in thread synchronization
6,138,210 Multi-stack memory architecture
6,125,439 Process of executing a method on a stack-based processor
6,101,580 Apparatus and method for assisting exact garbage collection by using a stack cache of tag bits
6,098,089 Generation isolation system and method for garbage collection
6,092,152 Method for stack-caching method frames
6,076,141 Look-up switch accelerator and method of operating same
6,067,602 Multi-stack-caching memory architecture
6,065,108 Non-quick instruction accelerator including instruction identifier and data set storage and method of implementing same
6,058,457 Method for storing method frames in multiple stacks
6,038,643 Stack management unit and method for a processor having a stack
6,026,485 Instruction folding for a stack-based machine
6,021,469 Hardware virtual machine instruction processor
6,014,723 Processor with accelerated array access bounds checking
5,970,242 Replicating code to eliminate a level of indirection during execution of an object oriented computer program
5,968,157 Locking of computer resources
5,953,736 Write barrier system and method including pointer-specific instruction variant replacement mechanism
5,925,123 Processor for executing instruction sets received from a network or from a local memory
5,873,105 Bounded-pause time garbage collection system and method including write barrier associated with a source instance of a partially relocated object
5,873,104 Bounded-pause time garbage collection system and method including write barrier associated with source and target instances of a partially relocated object
5,857,210 Bounded-pause time garbage collection system and method including read and write barriers associated with an instance of a partially relocated object
5,845,298 Write barrier system and method for trapping garbage collection page boundary crossing pointer stores
Pending Published US Patents
20230393788 Combined on-package and off-package memory system
20230315651 Application partitioning for locality in a stacked memory system
20230297499 Locating a memory unit associated with a memory address utilizing a mapper
20230297269 Hierarchical network for stacked memory system
20230275068 Memory stacked on a processor for high bandwidth
20230076872 Prefetch kernels on data parallel processors
20230043152 Memory interface with reduced energy transmit mode
20220374961 Techniques for performing matrix computations using hierarchical representations of sparse matrices
20220374496 Techniques for accelerating matrix multiplication computations using hierarchical representations of sparse matrices
20200242062 Reducing power and coupling noise on PAM-4 I/O interface