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The Able processor was designed in the mid-1970s for MSI components, and first assembled by New England Digital (NED, no connection to DEC) in a converted barn in Norwich VT. It was primarily used in embedded applications for experiment control and network processing. Its most successful application was in the Synclavier® digital synthesizer.

NED ceased operations in 1992, although a Synclavier® user consortium continued manufacturing for several years. Synclavier systems and support are still available from Synclavier.com.

The most notable feature of the Able processor is its single instruction - a MOVE from source to destination. Each instruction has an 8-bit source field and a 8-bit destination field. There is no opcode field. Arithmetic and control operations are encoded as special destinations. This makes the Able a transport-triggered architecture.

The Able had 16 16-bit registers. Memory references used a register for the address, with no addressing arithmetic. The PC was register 15, except in the interrupt state when it was register 14 (register 14 thus served as an interrupt handler pointer).

The Able bus transferred 16-bit data for 7-bit device addresses and 16-bit memory addresses. Bus transfers were asynchronous - the instruction would stall until the device acknowledged the transfer. For example, the single instruction which moved a character from the keyboard to the display would stall until a key was hit. In practice, devices included addresses for control and status registers to avoid such stalls. Late models of the Able, used in the Synclavier, added memory mapping registers to address several gigabytes of audio sample RAM.

Although an assembler syntax is shown below, the ABLE was programmed almost exclusively in XPL. All fields and register numbers here are in octal.


low byte high byte


bits use assembler notes
0------- Devices D0...D177
00000010 Priority Register D2 not in model B
00001000 Last Program Counter D10 not in model B
10------ Immediate IM(expression) expr in -32...+31
1100---- Register R0...R17
110i---- Register then Increment R0i...R17i reg++
1110---- Memory Source MR0...MR17 load M[reg]
1111---- Memory Source then Increment MR0i...MR17i load M[reg++]


bits use assembler notes
0------- Devices D0...D177
0000010 Encode Priority D2
0001000 Repeat D10
100----- Arithmetic acc op= SOURCE
100000-- Load LOA0...LOA3
100001-- And (&) AND0...AND3
100010-- Addition (+)
100011-- Subtract (-)
100100-- Exclusive Or (XOR)
100101-- Rotate Left (ROL)
100110-- OR (\)
100111-- Load Compliment (NOT)
1010---- Test test acc op= SOURCE
101000-- Load & Test TLOA0...TLOA3
101001-- And & Test TAND0...TAND3
101010-- Add & Test TADD0...TADD3
101011-- Subtract & Test TSUB0...TSUB3
101100-- Byte Swap with Or BSOR0...BSOR3
101101-- Shift Right with Add SHRA0...SHRA3
101110-- Add with Carry
101111-- Subtract with Borrow
1100---- Register R0...R17 reg = SOURCE
11010--- Conditional Transfer Absolute AT
11011--- Conditional Transfer Relative RT
1101-000 Always ATRA / RTRA
1101-100 Never ATNV / RTNV
1101-001 Zero ATZE / RTZE
1101-101 Non-zero ATNZ / RTNZ
1101-010 Carry ATRC / RTRC
1101-110 Non-carry ATNC / RTNC
1101-011 Minus ATMI / RTMI
1101-111 Non-minus ATPL / RTPL
1110---- Memory Destination MR0...MR17 M[reg] = SOURCE
1111---- Memory Destination then Inc MR0i-MR17i(ex.MR12) M[reg++] = SOURCE
11111010 Memory Destination then Dec MR12D M[R12--] = SOURCE

An attempt at re-implementation in VHDL is here. It runs under GHDL. On a Spartan 3 it occupies about 300 slices in addition to a BRAM for code/data. Instructions execute in a minimum of 3 clocks. The assembler uses an idiosyncratic syntax and hexademimal notation.

Synclavier® is a registered trademark of Cameron W. Jones and is used by permission.