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if-else vs case
if-else vs case
In the last hour we demonstrated how to design a 2:1 multiplexer with if-else and case. So one might think that logic constructed with if-else and case will be same always. But its not. Whenever we are going for more than 2 inputs in a multiplexer, then if-else and case creates different type of logic.
Take a look at the following code,
One might think that it will create a 4:1 multiplexer. However, this code creates a priority encoder, so it executes one condition after another. The circuit will look like this,
To create a 4:1 mux, we need to use the following VHDL with a case statement,
This code creates the ideal circuit that we were looking for,
Latch Inference:
Latch Inference:
We have to be very careful while writing the if-else and case statements. If they are not written properly, a latch can be created at the output. This latches can mess up the whole timing result. Therefore, the circuit might give wrong results at the output.
Sensitivity List
Sensitivity List
The sensitivity list includes all the signals that works as an input in a combinational process. The signals of the sensitivity list are included in the parentheses next to the process keyword in VHDL.
process(sensitivity list)
In the example given above, A,B,C,D and Selector are all input signals of the 4:1 multiplexer. Thats why all of them should be in the sensitivity list.
process(A,B,C,D,Selector)
Include all the input signals in the process sensitivity list for combinational logic
Failure to include all the input signals would result in a unwanted behavior in the simulation. This is one of the most common mistakes of VHDL.
If-Else
If-Else
This if-else is wrongly written,
process(state)
begin
if state = "001" then
cs <= "01";
elsif state = "010" then
cs <= "10";
elsif state = "100" then
cs <= "11";
end if;
end process;
Because, it did not specify each possible state. This will create output latches. The correctly written case statement would be,
process(state)
begin
if state = "001" then
cs <= "01";
elsif state = "010" then
cs <= "10";
elsif state = "100" then
cs <= "11";
else
cs <= "00";
end if;
end process;
Case
Case
This case statement is wrongly written,
process(state)
begin
case(state) is
when "001" =>
cs(0) <= '1';
when "010" =>
cs(1) <= '1';
when "100" =>
cs(1 downto 0) <= "11";
when others =>
cs(1 downto 0) <= "00";
end case;
end process;
Because, it did not specify all possible outputs for each state. This will create output latches. The correctly written case statement would be,
process(state)
begin
cs <= "00";
case(state) is
when "001" =>
cs(0) <= '1';
when "010" =>
cs(1) <= '1';
when "100" =>
cs(1 downto 0) <= "11";
when others =>
cs(1 downto 0) <= "00";
end case;
end process;
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