Its nearly impossible to put every VHDL code inside one entity while designing a huge design. Its also not a clever idea as a modular design helps to debug and ease the development.

So how can we divide a huge design in smaller parts and connect them together. Perhaps you have already guessed it? Yes, we will design smaller components of the bigger design as separate entities and connect them with a top entity.

Lets assume it is difficult to design nand and and gate together in a single entity (which is certainly not true :p, but for the sake of understanding just assume its right). We can develop two separate entities first. One for the nand gate and another for the and gate.

For example, an entity for the nand gate can be written as,

Now we want to put them together inside a top entity. The top entity would contain this two entities as components.

It might look intimidating in the beginning, but dont be scared. Its actually a pretty simple code. What we are doing here can be better understood by this diagram.

We are actually using the simple entities of NAND and AND inside this top entity here. We are declaring them as component after the architecture declaration.

Component Declaration:

Components are always declared after the architecture declaration and before the "begin" of the body of the architecture. The syntax is pretty same as the original entities. Only the term "entity" is replaced by the component here in the beginning.