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A major part of digital design is testing with simulation. A designer should never be satisfied if a VHDL code doesnt show any compilation or synthesis error. The design needs to be simulated with different inputs to see whether we are getting the correct output. The question is, how to simulate a circuit written in VHDL?
There comes the testbenches. A testbench is another entity that takes the design under test (DUT) as a component. In this hour, we will talk about testbenches written for combinational logics. We wrote an 8-bit adder in hour 5. The entity was written as,
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder_8bitc is
port (
A,B: in unsigned(7 downto 0);
C : out unsigned(8 downto 0) );
end adder_8bitc;
architecture adder_8bitc_arch of adder_8bitc is
begin
C <= resize(A+B,9);
end adder_8bitc_arch;
We want to test this circuit. So we need a testbench. We create an entity testbench_tb that doesnt have any input or output ports. This entity contains the adder_8bitc entity as a component. The input and output ports are connected to a few signals instantiated in the testbench_tb entity. We can feed these signals with different input values at different time instances and check the output. The code of the testbench is given below,
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench_tb is
end testbench_tb;
architecture testbench_arch of testbench_tb is
component adder_8bitc is
port (
A,B: in unsigned(7 downto 0);
C : out unsigned(8 downto 0) );
end component;
signal A: unsigned(7 downto 0) := (others=>'0');
signal B: unsigned(7 downto 0) := (others=>'0');
signal C: unsigned(8 downto 0) := (others=>'0');
begin
adder_8bi: adder_8bitc port map(
A => A,
B => B,
C => C);
process
begin
wait for 100 ns;
A <= "00000010";
B <= "00000011";
wait for 10 ns;
A <= "00000110";
B <= "00000101";
wait;
end process;
end testbench_arch;
In this case, we fed the inputs of adder_8bi with some values after 100ns. Then we wait for 10ns and feed next input values again. Afterwards, we wait indefinitely. Recall Hour 10, where we stated how behavioral codes use some extra features of VHDL language that are not supported for synthesis. The wait statements are not synthesizable. However, we dont also want to synthesize the testbench. We just want to use this part of the code for testing.
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After compiling the above code click on the "library" (circle 1)>click on "work" (circle 2)>click "testbench_tb" (circle 3) as the project name was that. Then you will find the architecture file. Right click on that and select "Simulate".
After Simulation a new simulation window will appear which looks like below:
To add waves of the input/output signals type "add wave *" (circle 1) at the bottom. "*" represents all waves of the logic. For observing the wave shapes for a certain period of time (e.g. 700 ns) type "run 700 ns" (circle 2). Shown below.
A separate window will appear containing the waves of the written logic (circle 3). If you click the button of circle 1 (toggle leaf names) you will see the name of the input/output signals (circle 2). Shown below.
You can zoom in and zoom out the signals by pressing I and O respectively.
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