Group Psychology, Sociology
UC Berkeley - Core Competencies and Behavioral Anchors
Stephen Covey - The Speed of Trust
Stephen Covey - The Seven Habits..
Portland's Sharing Economy
Stack ranking at Microsoft (Bloomberg, 8/26/2013
Stack ranking at GE vs. Microsoft (Forbes, July 2012)
Lectures by Daniel Kahneman (information about Kaheneman)
Basics of Bounded Rationality (Princeton pages)
Text on Rational Decision Making (boundless.com)
Bounded Rationality in decision making (Landa, 2001)
Computer Vision
Pedestrian Detection - Survey of State of the Art (Dollar, 2012)
Pedestrian Collision Avoidance Systems: A Survey of Computer Vision Based Recent Studies (Gandi, 2006)
Pedestrian Detection: A Benchmark (Dollar, 2009)
ImageNet Classification with Deep Convolutional Neural Networks (Krizhevsky, 2012)
In Vehicle Traffic Sign Detection and Recognition (Ruta, 2011)
3D Convolutional Neural Networks for Human Action Recognition (Ji, 2010)
Improving Neural Networks by Preventing co-Adaptation of Feature Detectors (Hinton, 2012)
Large Scale Sign Detection Using Hog Feature Variants (2011, Overett)
Aptina Image Sensors
Image Sensor World Blogspot
Fixed Pattern Noise (Wikipedia)
Fixed Pattern Noise (Yale lecture)
Embedded Systems
MISRA 2012 Coding Standards
Bus Architectures for Safety Critical Systems (Rushby, 2001)
Education of Embedded Software Engineers (Dewar, 2014)
Architecture of Safety Critical Embedded Systems (Kalinsky, 2009)
Safety Critical Operating Systems (Kliedermacher, 2001)
Advanced Course on Development of Safety Critical Systems (2012, Wilhelm)
Linux profiling tools
Chip Design
Sutherland - Synthesizing System Verilog
Verilog vs. VHDL - Cooley's Trial
System Verilog 3.1a LRM
Creating synthesizable VerilogDeepChip.com
Blocking and non-blocking assignments
Wilson Research Group study
Formal Verification methods at Intel
Lou Scheffer from Cadence on Timing Closure
UT 6306- front to back design of audio processor
OpenCores (OpenRISC processor)
Chip Design Magazines
High Frequency and Analog Stuff
Verilog-AMS Reference Manual from Designers-Guide.org
Verilog-AMS examples from EDA.org
Examples from the Designer's Guide to Verilog AMS
Silvaco - DFF example
The Designer's Guide to Verilog-AMS by Kundert and Zinke
OSU Paper on co-simulation
Spice Assertions
Analog Assertions
SystemVerilog test bench example
Mixed Signal Testing - invited tutorial
Great article from Dennis Fischette on PLL analysis
Modeling PLL's with Verilog/WREAL
An IEEE article on WREAL modeling of PLL's
Kundert on modeling PLL jitter
Silvaco on Modeling a PLL in Verilog-A
Floating ground planes and coupling
RAMBUS - verifying hi freq chip-chip interconnect
Shorting VIA arrays