International Conferences

  1. Jean-Luc Beuchat. Hardware Architectures for the Cryptographic Tate Pairing. In M. Abdalla and T. Lange, editors, Pairing-Based Cryptography–Pairing 2012, number 7708 in Lecture Notes in Computer Science. Springer, 2013. Invited talk. [slides]
  2. Nuray At, Jean-Luc Beuchat, and Ismail San. Compact Implementation of Threefish and Skein on FPGA. In Proceedings of the 5th IFIP International Conference on New Technologies, Mobility and Security. IEEE Press, 2012. [DOI] [Preprint version]
  3. Diego F. Aranha, Jean-Luc Beuchat, Jérémie Detrey, and Nicolas Estibals. Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves. In O. Dunkelman, editor, Topics in Cryptology–CT-RSA 2012, number 7178 in Lecture Notes in Computer Science, pages 98–115. Springer, 2012. [DOI] [Preprint version]
  4. Jean-Luc Beuchat, Eiji Okamoto, and Teppei Yamazaki. Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA. In J. Bian, Q. Zhou, and K. Zhao, editors, Proceedings of the 2010 International Conference on Field-Programmable Technology - FPT 2010, pages 170-177. IEEE Press, 2010. [DOI] [Preprint version]
  5. Jean-Luc Beuchat, Jorge Enrique González Díaz, Shigeo Mitsunari, Eiji Okamoto, Francisco Rodríguez-Henríquez, and Tadanori Teruya. High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves. In M. Joye, A. Miyaji, and A. Otsuka, editors, Pairing-Based Cryptography - Pairing 2010, number 6487 in Lecture Notes in Computer Science, pages 21-39. Springer, 2010. [DOI] [Preprint version]
  6. Jean-Luc Beuchat, Emmanuel López-Trejo, Luis Martínez-Ramos, Shigeo Mitsunari, and Francisco Rodríguez-Henríquez. Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves. In J.A. Garay, A. Miyaji, and A. Otsuka, editors, Cryptology and Network Security - CANS 2009, number 5888 in Lecture Notes in Computer Science, pages 413-432. Springer, 2009. [DOI] [Preprint version]
  7. Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, and Francisco Rodríguez-Henríquez. Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers. In C. Clavier and K. Gaj, editors, Cryptographic Hardware and Embedded Systems - CHES 2009, number 5747 in Lecture Notes in Computer Science, pages 225-239. Springer, 2009. Best Paper Award. [DOI] [Preprint version]
  8. Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, and Francisco Rodríguez-Henríquez. A Comparison Between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m. In S.D. Galbraith and K.G. Paterson, editors, Pairing 2008, number 5209 in Lecture Notes in Computer Science, pages 297-315. Springer, 2008. [DOI] [Preprint version]
  9. Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, and Eiji Okamoto. Arithmetic Operators for Pairing-Based Cryptography. In P. Paillier and I. Verbauwhede, editors, Cryptographic Hardware and Embedded Systems - CHES 2007, number 4727 in Lecture Notes in Computer Science, pages 239-255. Springer, 2007. Best Paper Award. [DOI] [Preprint version]
  10. Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, and Eiji Okamoto. A Coprocessor for the Final Exponentiation of the ηT Pairing in Characteristic Three. In C. Carlet and B. Sunar, editors, Proceedings of WAIFI 2007, number 4547 in Lecture Notes in Computer Science, pages 25-39. Springer, 2007. [DOI] [Preprint version]
  11. Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, and Eiji Okamoto. An Algorithm for the ηT Pairing Calculation in Characteristic Three and its Hardware Implementation. In P. Kornerup and J.-M. Muller, editors, Proceedings of the 18th IEEE Symposium on Computer Arithmetic, pages 97-104, IEEE Computer Society, 2007. [DOI] [Preprint version]
  12. Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, and Eiji Okamoto. Multiplication over Fpm on FPGA: A Survey. In P.C. Diniz, E. Marques, K. Bertels, M.M. Fernandes, and J.M.P. Cardoso, editors, Reconfigurable Computing: Architectures, Tools and Applications - Proceedings of ARC 2007, number 4419 of Lecture Notes in Computer Science, pages 214-225. Springer, 2007. [DOI]
  13. Rachid Beguenane, Jean-Luc Beuchat, Jean-Michel Muller, and Stéphane Simard. Modular Multiplication of Large Integers on FPGA. In Proceedings of the 39th Asilomar Conference on Signals, Systems & Computers, pages 1361-1365. IEEE Signal Processing Society, 2005. [DOI]
  14. Jean-Luc Beuchat and Jean-Michel Muller. Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Numbers. In S. Vassiliadis, N. Dimopoulos, and S. Rajopadhye, editors, Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pages 303-308. IEEE Computer Society, 2005. [DOI]
  15. Jean-Luc Beuchat. FPGA Implementations of the RC6 Block Cipher. In P.Y.K. Cheung, G.A. Constantinides, and J.T. de Sousa, editors, Field-Programmable Logic and Applications, number 2778 of Lecture Notes in Computer Science, pages 101-110. Springer, 2003 [DOI]
  16. Jean-Luc Beuchat, Laurent Imbert, and Arnaud Tisserand. Comparison of Modular Multipliers on FPGAs. In F.T. Luk, editor, Advanced Signal Processing Algorithms, Architectures and Implementations XIII, volume 5205, pages 490-498. The International Society for Optical Engineering (SPIE), 2003. [DOI]
  17. Jean-Luc Beuchat. Modular Multiplication for FPGA Implementation of the IDEA Block Cipher. In E. Deprettere, S. Bhattacharyya, J. Cavallaro, A. Darte, and L. Thiele, editors, Proceedings of the 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pages 412-422. IEEE Computer Society, 2003. [DOI]
  18. Jean-Luc Beuchat. Some Modular Adders and Multipliers for Field Programmable Gate Arrays. In Proceedings of the 17th International Parallel & Distributed Processing Symposium. IEEE Computer Society, 2003. [DOI]
  19. Jean-Luc Beuchat and Arnaud Tisserand. Small Multiplier-based Multiplication and Division Operators for Virtex-II Devices. In M. Glesner, P. Zipf, and M. Renovell editors, Field-Programmable Logic and Applications - Reconfigurable Computing Is Going Mainstream, number 2438 in Lecture Notes in Computer Science, pages 513-522. Springer, 2002. [DOI]
  20. Jean-Luc Beuchat and Eduardo Sanchez. An On-Line Arithmetic-Based Reconfigurable Neuroprocessor. In J. Rolim, editor, Parallel and Distributed Processing, number 1586 in Lecture Notes in Computer Science, pages 700-702. Springer, 1999. [DOI]
  21. Jean-Luc Beuchat and Eduardo Sanchez. Using On-Line Arithmetic and Reconfiguration for Neuroprocessor Implementation. In J. Mira and J.V. Sánchez-Andrés, editors, Engineering Applications of Bio-Inspired Artificial Neural Networks, number 1607 in Lecture Notes in Computer Science, pages 129-138. Springer, 1999. [DOI]
  22. Jean-Luc Beuchat, Jacques-Olivier Haenni, and Eduardo Sanchez. Hardware Reconfigurable Neural Networks. In J. Rolim, editor, Parallel and Distributed Processing, number 1388 in Lecture Notes in Computer Science, pages 91-98. Springer, 1998. [DOI]
  23. Jean-Luc Beuchat and Eduardo Sanchez. A Reconfigurable Neuroprocessor with On-chip Pruning. In L. Niklasson, M. Bodén, and T. Ziemke, editors, Perspectives in Neural Computing - ICANNN 1998, pages 1159-1164. Springer, 1998.