Self Healing SoC

SHF: Medium: Collaborative Research: System Level Self Correction Using On-Chip Micro Sensor Network and Autonomous Feedback Control

NSF (CCF-0964634)

Professors: Byunghoo Jung (PI) & Kaushik Roy

Students (Prof. Jung's): Jangjoon Lee & Srikar Bhagavatula

[ Vision ]

Device parameter variations have emerged as a major challenge in system design using nanoscale technologies. Such variations are caused by fundamental physical limitations associated with nanofabrication processes as well as temporal deviations in device parameters due to environmental effects (such as temperature) and device aging. Process-induced and temporal parameter variations are becoming major bottleneck to achieve low-power dissipation and high parametric yield. Design techniques to simultaneously achieve variation tolerance and low-power operation typically have conflicting requirements. The research aims at developing systematic, robust and generic automatic correction techniques for SoC design to achieve consistent performance and power dissipation among the fabricated SoCs in the presence of severe process, environmental and device aging-induced variations. It addresses auto-correction of digital and analog building blocks of SoC using low-overhead integrated sensors distributed over the system and efficient compensation mechanisms following a generic feedback controller (open/closed loop).

[ Publications ]

1. J. Lu, W. Loke, and B. Jung, "mm-Wave Wireless Interconnect in 3-D SIC for Post-bond Testing,” IEEE Design & Test of Computers. (submitted).

2. S. Bhagavatula and B. Jung, "A Power Sensor with 80ns Response Time for Power Management in Microprocessors," IEEE Custom Integrated Circuits Conference, Sept. (2013). {SLIDES}

3. J. Lee, S. Bhagavatula, K. Roy, and B. Jung, "Variation-aware and Self-healing Design Methodology for a System-on-chip," 13th IEEE Latin American Test Workshop, April (2012). {SLIDES}

4. S. Bhagavatula and B. Jung, "A Low Power Real-time On-chip Power Sensor in 45nm SOI", IEEE Transactions on Circuits and Systems I, pp. 1157-1587, vol. 59, (2012).

5. J. Lee, S. Bhagavatula, S. Bhunia, K. Roy and B. Jung, "Self-healing Design in Deep Scaled CMOS Technologies", J. of Circuits, Systems, and Computers, pp. 1240011-1 - 1240011-15, vol. 21, (2012).

6. N. Seetharam, K. Keerthi, and B. Swarup, "Healing of DSP Circuits under Power Bound Using Post-Silicon Operand Bitwidth Truncation", IEEE Transactions on Circuits and Systems I, pp. 1932-1941, vol. 59, (2012).

7. J. Lee, S. Bhagavatula, K. Roy, B. Jung, “Self-Healing Design In Deep Scaled CMOS Technologies (Invited Paper)," 54th IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), Aug. (2011). {SLIDES}

8. W. Chen, W. Loke and B. Jung, “A PVT-Tolerant, Ultra-Low-Power Phase-Locked Loop for Wireless Implantable Biomedical Devices (Invited Paper),” 54th IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), Aug. (2011). {SLIDES}

9. G. Panagopolous and K. Roy, "A 3-D Physical Model for Vth Variations Considering the Combined Effect of NBTI and RDF", IEEE Transactions on Electron Devices, pp. 2337-2346, vol. 58, (2011).

10. G. Panagopoulos and K. Roy, "A Physics-Based Three-Dimensional Analytical Model for RDF-Induced Threshold Voltage Variations", IEEE Tran. on Electron Devices, pp. 392-403, vol. 58, (2011).

11. S. Bhunia and R. Rao, "Guest Editors' Introduction: Managing Uncertainty through Postfabrication Calibration and Repair", IEEE Design & Test of Computers, pp. 4-5, vol. 27, (2010).

12. W. Chen and B. Jung, "Self-Healing Phase-Locked Loops in Deep-Scaled CMOS Technologies", IEEE Design & Test of Computers, pp. 18-25, vol. 27, (2010).