Z80 test layout 1

This is the first test of the Z80 with RAM and a basic I/O output minimum logic used.

No address decoding used for RAM or I/O, using the Z80's MREQ and IOREQ and logic to decode when to read and write.

Sample program to put Alpha numeric numbers on Seven Segment display. No delays needed since I used a software to drive the clock, as to be able to watch it count up and go through code.

.area CODE1 (ABS)

.org 0H0000

main1$: ld hl, table1

ld c, 0h0f

loop1$: ld a, (hl)

out (0h01),a

inc hl

dec c

jp Z, main1$

jp loop1$

table1: .byte 0h3f

.byte 0h06

.byte 0h5b

.byte 0h4f

.byte 0h66

.byte 0h6d

.byte 0h7d

.byte 0h07

.byte 0h7f

.byte 0h6f

.byte 0h77

.byte 0h7c

.byte 0h39

.byte 0h5e

.byte 0h79

.byte 0h71

.byte 0h00

Video of the code in action, breadboard version