NYCU
CEreal and REliable SoC Laboratory
Welcome to Cerebral and Reliable SoC Laboratory (CERES Lab). Prof. Kun-Chih Chen is the PI and the lab location is at Engineering Building D Room 428, NYCU. CERES Lab aims to integrate interdisciplinary research and develop any key techniques for advanced VLSI systems, including AI accelerator design, reliable system design, smart manufacturing, etc. More details can be found in (Lab Overview). Sincerely welcome to join us!!
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Hot News!!!
Congratulation on the 2024 IEEE TVLSI Best Paper Award to Mr. Yuan-Hao Liao, Mr. Cheng-Ting Chen and Ms. Lei-Qi Wang
Mr. Pavan Kumar MP's, Ms. Lai-Chi Wang's and Mr. Wei-Ren Syu's Funding at international academic conferences by graduate students applications are approved
Congratulation on the acceptance of Mr. Pavan Kumar MP and Mr. Zhe-Xiang Tu's IEEE AICAS'24 paper
Congratulation on the acceptance of Prof Jimmy Chen's VLSI TSA'24 paper
Congratulation on the elected exemplary teaching materials development in 2023 MOE project