Welcome to Cerebral and Reliable SoC Laboratory (CERES Lab). Prof. Kun-Chih Chen is the PI and the lab location is at Engineering Building D Room 428, NYCU. CERES Lab aims to integrate interdisciplinary research and develop any key techniques for advanced VLSI systems, including AI accelerator design, reliable system design, smart manufacturing, etc. More details can be found in (Lab Overview) (Open-house Video). Sincerely welcome to join us!!
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Congratulation on the winner of Mr. Yen-Chen Yen, Ms. Tsu-Chiao Chen, Ms. Chia-Hsuan Mi, and Mr. Sheng-Chuan Pai's 2025 FPGA Innovative AI Edge Node Computing Contest - Merit Award
Congratulation on the honor of Prof. Jimmy's Chen's NYCU Excellent Tutor Award
Congratulation on the acceptance of Mr. Pin-Ching Shen and Bo-Chun Chen's APSIPA ASC'25 paper
Congratulation on the acceptance of Ms. Chia-Hsuan Mi, Tsu-Ping Lin, and Tsu-Chiao Chen's IEEE APCCAS'25 paper
Prof. Jimmy was selected as the Ambassador of IEEE Day 2025