ABOUT LAB

Cerebral and Reliable SoC Laboratory (CERES Lab.) originally is a newly built laboratory in the Department of Electronic Engineering of Feng Chia University in 2015. Dr. Kun-Chih Chen is the advisor. Then, CERES Lab. is re-built in the Department of Computer Science and Engineering of National Sun Yat-Sen University (NSYSU) in 2016 and in the Institute of Electronics of National Yang Ming Chiao Tung University (NYCU) in 2023. CERES Lab. is currently located at Engineering Building D Room ED428. The main hardware equipment for RD works are workstation, PC, and FPGA, software equipment are programming languages (e.g., Verilog, C++, System C, MATLAB, etc.) and CAD tools (e.g., ModelSim, Synopsys, Design Compiler, Cadence Tools, etc.).

        In terms of research, to cope with the technology scaling down and multicore development, CERES Lab. establish and develop the key techniques for the advanced VLSI system by interdisciplinary linking Thermodynamics, Heat Transference, Queueing Theory, Game Theory, Digital Signal Processing, VLSI Architecture Implementation, etc.. CERES Lab. focus on the development of the following techniques.

       Although the CERES Lab. is a new laboratory in National Yang Ming Chiao Tung University, its focus research issues are the hot topics in the industry and academia. CERES is also a goddess in Greek mythology, teaches the people farming and make them can self-sufficient to handle the future challenges, which is also consistent with the spirit of this lab.. Through the MS/PhD training, CERES Lab. will comprehensively provide the students practical and theoretical training to meet the need of the future rapidly changing ICT industry. We anticipate the students can have independent and innovative thinking after leaving from the lab.. If you are interested in our research spectrum and direction, please contact Prof. Chen. Sincerely welcome to join us!!