Journal Publication

Total : 109

2024 (6)

1. S. Bhattacharya, A. Kundu, S. D. Nair, A. Chakraborty, A. Sarkar & M. Mukherjee, "Design and analysis of photo-electrical characteristics of graphene/Si-nanowire photo-detector: a potential photo-detector for applications in IR detection",  Microsystem Technologies, 2024, https://doi.org/10.1007/s00542-024-05687-y 

2. S Datta, A. Deyasi, A. Basak, and A. Sarkar, (2024) “Impact of nanometric buried Oxide layer on subthreshold swing and drain conductance of junctionless accumulation mode MOSFET for analog circuit applications”. International Journal of Nano Dimension (Int. J. Nano Dimens.). Vol. 15, No. 2,  Available at: https://doi.org/10.57647/j.ijnd.2024.1502.12. 

3. A Kundu, JC Das, B Debnath, D De, A Sarkar, Design of Reversible Quantum Vigenere Cryptographic Cipher in QCA and IBMQ Platforms for secure Nanocommunication, NANO, https://doi.org/10.1142/S1793292024500139 

4. J Chowdhury, A Sarkar, K Mahapatra, JK Das, "More-than-Moore Steep Slope Devices for Higher frequency Switching Applications: A Designer’s Perspective", Physica Scripta

5. A Kundu, JC Das, B Debnath, D De, A Sarkar, "Secure nano-communication framework using RSCV cryptographic circuit in IBM Q", Physica Scripta,  99 (1), 015116

6. M Mukherjee, N Ghosh, P Debnath, A Sarkar, M Chanda "Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications", Journal of Integrated Circuits and Systems 19 (1), 1-7

2023 (8)

1. T. Ganguli, M. Chanda and A. Sarkar, "Impact of Aspect Ratio and Interface Trap Charge on the Performances of Junctionless MOSFET-Based Adiabatic Logic Circuit," in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2023.3327348.

2. P Sriramani, N Mohankumar, Y Prasamsha, A Sarkar, M Chanda, "Threshold and surface potential-based sensitivity analysis of symmetrical double gate AlGaN/GaN MOS-HEMT including capacitance effects for label-free biosensing", Physica Scripta, IOP, October 2023 

3. S Dey, PK Roy, A Sarkar, "Adaptive IIR model identification using chaotic opposition-based whale optimization algorithm", Journal of Electrical Systems and Information Technology, Springer, 10 (1), 33, 2023

4. S. Bhattacharya, A. Kundu, D. Chakraborty, A. Sarkar and M. Mukherjee, "Strain Modulated Asymmetrical Si/SiGe Superlattice p+-i-n+ Switches for MMW Low-Loss Secure Communication Systems," in IEEE Transactions on Device and Materials Reliability, 2023 Mar 1;23(1):14-26. , doi: 10.1109/TDMR.2022.3224444.

5. A BASAK, A Deyasi, A Sarkar,"2D Analytical Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET for Biosensing Applications considering Steric Hindrance Issue", Physica Scripta, April, 2023, DOI 10.1088/1402-4896/accbf3 

6. S Sinha, T Paul, S Mishra, S Shaw, K Biswas, D De, A Sarkar "Correction: In Vivo Biointeraction and Alleviation of Toxicity of MWCNTs upon Functionalization with ssDNA in a Caenorhabditis elegans Model", Journal of Electronic Materials, 52, page 2894 (2023) 

7. A. Deyasi, S. Chakrabarti, P. Bharti, K. Majee, S. Roy and A. Sarkar , "Performance Improvement of CISSe Solar Cell Through CuI Back Layer and Optimized Device Structure", JAPED, 17.2, p. 135-144, 

8. A. Kundu, J. C. Das, B. Debnath, D. De, and A. Sarkar, ‘Secure nano-communication framework using RSCV cryptographic circuit in IBM Q’, Physica Scripta, vol. 99, no. 1, p. 015116, Dec. 2023.

2022 (5)

1. M. Mukherjee, S. Guha, P. Debnath, A. Sarkar & M. Chanda, "Analytical Modelling of Dopingless (DL) Impact Ionization MOSFET (IMOS)", Silicon, 14, 11493–11501 (2022). 

2. R. Ghoshhajra, K. Biswas, A. Sarkar, "Device Performance Prediction of Nanoscale Junctionless FinFET Using MISO Artificial Neural Network ", Silicon, 14, 8141–8150 (2022). 

3. T Ganguli, M Chanda & A Sarkar, "Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime", Computers and Electrical Engineering, 100, 107914

4. J Chowdhury, A Sarkar, K Mahapatra & JK Das, "Analytical modeling of dielectrically modulated broken-gate tunnel FET biosensor considering partial hybridization effect", Computers & Electrical Engineering, 99, 107859

5. N Chand, S Adak, SK Swain, SM Biswal, A Sarkar, "Performance enhancement of normally off InAlN/AlN/GaN HEMT using aluminium gallium nitride back barrier", Computers & Electrical Engineering 98, 107695

2021 (13)

1. A Deyasi, AK Bhattacharjee, S Mukherjee, A Sarkar, "Multi-layer Perceptron based Comparative Analysis between CNTFET and Quantum Wire FET for Optimum Design Performance", Solid State Electronics Letters 3, 42-52

2. A Deyasi, R Ghosh, P Chakraborty, A Adhikary, A Sarkar, "Investigating Fill Factor Effect on Brillouin Zone of Metamaterial-Based 2D Photonic Crystal", Micro and Nanosystems 13 (4), 433-441 

3. K Biswas, A Sarkar, CK Sarkar, "Linearity and Analog Performance Analysis of Silicon Junctionless Bulk FinFET Considering Gate Electrode Workfunction Variability and Different Fin Aspect Ratio", Silicon, 1-10

4. P. Debnath, A. Deaysi, U. Mondal, A. Sarkar, "Analytical investigation of double negative material based photonic filter performance at 1550 nm",  JOURNAL OF OPTOELECTRONICS AND ADVANCED MATERIALS, Vol. 23, No. 7-8, July – August 2021, p. 319 - 326 

5. S Sinha, T Paul, S Mishra, S Shaw, K Biswas, D De, A Sarkar, In Vivo Biointeraction and Alleviation of Toxicity of MWCNTs upon Functionalization with ssDNA in a Caenorhabditis elegans Model, Journal of Electronic Materials, Springer, 1-17

6. P Mitra, J Bhaumik, A Sarkar, Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip, Journal of Electronic Testing, Springer, 1-5

7. S Misra, SM Biswal, B Baral, SK Swain, A Sarkar, SK Pati, Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry, Journal of Computational Electronics, Springer, 20 (1), 480-491

8. B Das, N Chand, A Sarkar, Review the Performance of Different Digital Modulation Techniques with Suitable Error Control Codes in Telehealth Services, Advances in Medical Physics and Healthcare Engineering, 341-352

9. N Chand, S Bhattacharyya, A Sarkar, A Novel Encryption Technique to Protect Patient Health Information Electronically Using Playfair Cipher 15 by 14 Matrix, Advances in Medical Physics and Healthcare Engineering, 423-431

10. R Dhar, A Deyasi, A Sarkar, Analysis of Optical Performance of Dual-Order RAMAN Amplifier Beyond 100 THz Spectrum, Advanced Materials for Future Terahertz Devices, Circuits and Systems 727, 193

11. A Deyasi, A Sarkar, Performance Estimation of Defected Ternary Photonic Crystal-Based Bandpass Filter Beyond 100 THz for All-Optical Circuit, Emerging Trends in Terahertz Engineering and System Technologies: Devices 

12. A Deyasi, N Pramanik, A Sarkar, Detecting Signature of Virus Using Metamaterial-Based One-Dimensional Multi-layer Photonic Crystal Structure Under Polarized Incidence, Modern Techniques in Biosensors, 199-214

13. A Deyasi, S Bhattacharyya, P Debnath, A Sarkar, Authentic Pedagogy: A Project-Oriented Teaching–Learning Method Based on Critical Thinking, Computational Intelligence in Digital Pedagogy, 1-20

2020 (13)

1. J Chowdhury, A Sarkar, K Mahapatra, JK Das, Novel center potential based analytical sub-threshold model for dual metal broken gate TFET, Circuit World, Emereld Insight 

2. Arighna Basak, Angsuman Sarkar, Drain current modelling of asymmetric junctionless dual material double gate MOSFET with high K gate stack for analog and RF performance, Silicon, 1-12, Springer, 2020/11/10

3. P Mitra, A Sarkar, "Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip", Journal of Electronic Testing, 1-5, 2020, Springer 

4. S. Misra, S. M. Biswal, B. Baral, S. K. Swain, A. Sarkar & S. K. Pati, "Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry", Journal of Computational Electronics (2020), Published: 15 September 2020, Springer 

5. A. Basak & A. Sarkar, ' Quantum Analytical Model for Lateral Dual Gate UTBB SOI MOSFET for Analog/RF Performance', Silicon (2020), Springer 

6. S Sinha, S Shaw, K Biswas, D De, SC Das, A Sarkar, J Bandyopadhyay, 'Favorable influence of ssDNA-functionalized SWCNT on the navigation pattern of C. elegans', Microsystem Technologies, 1-14, June 2020, Springer

7. A. Deyasi, U. Dey, S. Das, S. De & A. Sarkar, “Computing Photonic Bandgap from Dispersion Relation for TM Mode Propagation Inside Metamaterial-based 1D PhC”, Micro and Nanosystems (2020) 12: 1., Bentham Science 

8. M. Mukherjee, M. Chanda, A. Sarkar & A. Dey, "Effect of band non-parabolicity on energy sub-band profile for nano-dimensional MOSFET", Microsystem Technologies, Springer, Feb 2020 

9. A. Deyasi, S. Mukherjee, A. K. Bhattacharjee and A. Sarkar "Classification of single and double-gate nanoscale MOSFET with different dielectrics from electrical characteristics using soft computintechniques", International Journal of Information Technology, Online first 05-Apr, 2019,DOI https://doi.org/10.1007/s41870-019-00301-1, Published by Springer 

10. A. Deyasi, A. Sarkar, "Effect of material composition on noise performance of sub-micron high electron mobility transistor", Microsystem Technologies, 28, 577–585 (2022). 

11. A Bhattacharya, A Maity, D Bhardwaj, S Banerjee, D De, A Sarkar, S Bari, Design of High Speed and Low-Power NOR Based Dynamic CMOS PLA for Logic Function Realization, https://dx.doi.org/10.2139/ssrn.3518279, Available at SSRN 3518279 

12. A Deyasi, G Saha, B Sen, A Sarkar, 'Computation of Subthreshold Slope in Submicron-HEMT for Different Structural Parameters with Parasitic Effects'  - Nanomaterials and Energy, 15/7/2020

13. Arighna Basak, Angsuman Sarkar, Impact of back gate work function for enhancement of analog/RF performance of AJDMDG Stack MOSFET, Solid State Electronics Letters, Vol. 2, pp. 117-123, 2020/12/1

2019 (6)

1. A. Deyasi, and A. Sarkar, "Calculating Current Density and Quantum Efficiency of p-n Junction Solar Cell with Quasi-Fermi Level approximation", International Journal of Nanoparticles [Inderscience], vol. 11, No. 1, pp. 27-36, 2019 [DOI: 10.1504/IJNP.2019.097923]

2. S. Paul, S. Mondal, & A. Sarkar, "Characterization and analysis of low-noise GaN-HEMT based inverter circuits", Microsystem Technologies, Springer, Online First on 20-Aug-2019

3. A Deyasi, A Sarkar, Effect of temperature on electrical characteristics of single electron transistor, Microsystem Technologies, Springer Berlin Heidelberg, 25(5), 1875-1880, May 2019

4. JK Mandal, A Sarkar, Special Issue on the 2nd International Conference Devices for Integrated Circuits (DevIC-2017), Microsystem Technologies 25 (5), 1853-1853 

5. A. Basak, M. Chanda, A. Sarkar, Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications, Microsystem Technologies, DOI: 10.1007/s00542-019-04691-x 

6. A Deyasi, A Sarkar, K Roy, AR Chowdhury, Effect of high-K dielectric on differential conductance and transconductance of ID-DG MOSFET following Ortiz-Conde model, Microsystem Technologies, Springer

2018 (7)

1. A. Deyasi, A. Sarkar, Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method, International Journal of Electronics, Taylor& Francis Group, UK, Published online: 14 Jul 2018

2. Kalyan Biswas ; Angsuman Sarkar ; Chandan Kumar Sarkar, Effect of Varying Indium Concentration of InGaAs Channel on Device and Circuit Performance of Nanoscale Double Gate Heterostructure MOSFET, Micro & Nano Letters, IET, UK, Available online: 05 February 2018

3. S Sinha, K Biswas, S Shaw, D De, A Sarkar, J Bandyopadhyay, Conductivity Modulation of SWCNT by Its Sidewall Functionalization Through Heavily Doping with DNA Nucleobase Adenine, Materials Focus, American Scientific Publishers, Vol. 7, No. 1,  pp. 11-17

4. K Biswas, A Sarkar, CK Sarkar, Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs, Microsystem Technologies, Springer Berlin Heidelberg, 1-8, First Online: 18 January 2018

5. A Deyasi, A Sarkar, Variation of optical bandwidth in defected ternary photonic crystal under different polarisation conditions, International Journal of Nanoparticles,  Inderscience Publishers,10 (1-2), 27-34

6. A Chakraborty, D Singha, A Sarkar, Staggered heterojunctions-based tunnel-FET for application as a label-free biosensor, International Journal of Nanoparticles, Inderscience Publishers,  10 (1-2), 107-116

7. A. Deyasi, P. Verma, P. Paul, and A. Sarkar, "Effect of Nanoscale Dimension on Characteristic Impedance of MIM Surface Plasmon Structure", Journal of Active and Passive Electronic Devices, vol. 13(2-3), pp. 195-207, 2018 [ISSN: 1555-029x, ESCI Journal]

2017 (9)

1. Avik Chakraborty, Angsuman Sarkar, Analytical modeling and sensitivity analysis of dielectric-modulated junctionless gate stack surrounding gate MOSFET (JLGSSRG) for application as biosensor, Journal of Computational Electronics, Springer, vol. 16, no. 3, 556-567

2. Sudhansu Mohan Biswal, Biswajit Baral, Debashis De, A Sarkar, Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET, Microsystem Technologies,  Springer Berlin Heidelberg, pp. 1-7, First Online: 04 December 2017

3. Biswajit Baral,Sudhansu Mohan Biswal,Debashis De,Angsuman Sarkar, Effect of gate-length downscaling on the analog/RF and linearity performance of InAs-based nanowire tunnel FET, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 30. No. 3-4,DOI: 10.1002/jnm.2186

4. Biswajit Baral, Sudhansu Mohan Biswal, Debashis De, Angsuman Sarkar, Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor, SIMULATION, Vol 93, Issue 11, pp. 985 - 993, DOI: https://doi.org/10.1177/0037549717704308

5. K Biswas, A Sarkar, CK Sarkar, Assessment of Dielectrics and Channel Doping Impact in Nanoscale Double Gate III–V MOSFET with Heavily Doped Source/Drain Region, Materials Focus, vol. 6, No. 2, pp. 116-120, American Scientific Publishers

6. Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar, Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs, IET Circuits, Devices & Systems, vol. 11, No. 1, pp. 80-88

7. Surajit Bari, Debashis De, Angsuman Sarkar, Design of low power, high speed 4 bit binary to Gray converter with 8 × 4 barrel shifter using nano dimensional MOS transistor for arithmetical, logical and telecommunication circuit and system application, Microsystem Technologies, DOI: 10.1007/s00542-017-3435-4

8. S Sinha, K Biswas, D De, J Bandyopadhyay, A Sarkar, Metal to semimetal conversion by band structure engineering of SWCNT by DNA nucleobase functionalization, Microsystem Technologies, 1-8, 2017

9. S Bari, S Bhowmik, D De, A Sarkar, Design and power analysis of 4× 4 semiconductor ROM array with row decoder and column decoder at 32, 22 and 16 nm channel length of MOS transistor, Microsystem Technologies, Springer Berlin Heidelberg,  vol. 23, No. 9, pp. 4237-4243

2016 (12)

1. Angsuman Sarkar and Chandan Kr. Sarkar "Triple Material Surrounding Gate MOSFET for Suppression of SCEs", Reason- A Technical Journal, Volume-25, pp. 1-8, ISSN No. 2277-1654, DOI:10.21843/reas/2015/1-8/108322

2. Kalyan Biswas, Angsuman Sarkar, and Chandan Kumar Sarkar "Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET", ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 12, no. 4, Article 36 (May 2016), 12 pages. DOI=http://dx.doi.org/10.1145/2903143, 2016

3. Sudhansu Mohan Biswal, Biswajit Baral, Debashis De, Angsuman Sarkar, "Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET", Superlattices and Microstructures, Volume 91, March 2016, Pages 319-330, ISSN 0749-6036, http://dx.doi.org/10.1016/j.spmi.2016.01.021.

4. S. Sinha, K. Biswas, T. Purkayastha, J. Banyopadhyay, A. Sarkar, and D. De, "On the Electronic Properties of Guanine Functionalized Zigzag Single-Walled Carbon-Nanotube", Journal of Nanoengineering and Nanomanufacturing, American Scientific Publishers, USA, Vol. 6, pp. 1–6, 2015, doi:10.1166/jnan.2015.1259

5. Surajit Bari, Arunima Maity, Debashis De, Angsuman Sarkar, Average Power Consumption and Delay Analysis of Schmitt Trigger Circuit using Low Dimensional MOS Transistor,Advances in Industrial Engineering and Management, American Scientific Publishers,Vol. 5, No. 1, pp. 85-88, doi: 10.7508/aiem.2016.01.017, published online 01 Jul 2016

6. Surajit Bari, Arunima Maity, Debashis De, Angsuman Sarkar, Design and Average Power Consumption Analysis of 3-Stage CMOS Ring Oscillator Circuit at 32 nm Channel Length, Advances in Industrial Engineering and Management, American Scientific Publishers,Vol. 5, No. 1, pp. 89-92, doi: 10.7508/aiem.2016.01.018, published online 01 Jul 2016

7. Abhishek Chakraborty, Sourav Bairagya, Angsuman Sarkar, Analytical Model of Surface Potential of Double Surrounding Gate MOSFET, Advances in Industrial Engineering and Management, American Scientific Publishers, vol. 5, no. 1, 2016, pp. 93-97, doi: 10.7508/aiem.2016.01.019, published online 01 Jul 2016

8. Kakali Sarkar, Angsuman Sarkar, Analytical Modeling of Junction-Less Surrounding Gate MOSFET Based Biosensor, Advances in Industrial Engineering and Management, American Scientific Publishers, vol. 5, no. 1, 2016, pp. 98-102, doi: 10.7508/aiem.2016.01.020, published online 01 Jul 2016.

9. Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar, Effect of Gate Dielectrics on Simulated Device Characteristics of Nanoscale Double Gate Heterostructure MOSFET, Advances in Industrial Engineering and Management, American Scientific Publishers, vol. 5, no. 1, 2016, pp. 113-117, doi: 10.7508/aiem.2016.01.023, published online 01 Jul 2016.

10. Biswajit Baral, Sudhansu Mohan Biswal, Jagruti Padhee, Debashis De, Angsuman Sarkar, Effect of Gate Length Downscaling on RF/Analog and Linearity Performance of a Junctionless Double Gate MOSFET for Analog/Mixed Signal System-On-Chip Applications & It’s Comparative Study with Conventional Mosfet, Advances in Industrial Engineering and Management, American Scientific Publishers, vol. 5, no. 1, 2016, pp. 130-137, doi: 10.7508/aiem.2016.01.026, published online 01 Jul 2016.

11. Sudhansu Mohan Biswal, Biswajit Baral, Debashis De, Angsuman Sarkar, Analog/RF performance and Linearity Investigation of Si-based Double Gate Tunnel FET, Advances in Industrial Engineering and Management, American Scientific Publishers, vol. 5, no. 1, 2016, pp. 150-156, doi: 10.7508/aiem.2016.01.029, published online 01 Jul 2016.

12. Avik Chakraborty, Angsuman Sarkar, “Two-dimensional analytical model of asymmetric dual Material double-gate MOSFET”, Advances in Industrial Engineering and Management” Vol. 5, No. 2, pp. 178-182, (2016), doi: 10.7508/178 aiem.2016.02.002, ISSN: 2222-7059 (print), ISSN: 2222-7067 (online), http://www.aspbs.com/aiem (American Scientific Publisher)

2015 (8)

1. Kalyan Biswas, Angsuman Sarkar, C. K. Sarkar "Impact of barrier thickness on Analog, RF & Linearity performance of Nanoscale DG Heterostructure MOSFET", Superlattices and Microstructures, Volume 86, Page: 95-104, October 2015 © Elsevier B.V, Impact Factor: 2.097

2. Surajit Bari, Debashish De, Angsuman Sarkar, "Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study", Physica E: Low-dimensional Systems and Nanostructures, Vol. 67, Page: 143-151, March 2015, © Elsevier B.V, Impact Factor: 2.00

3. Avik Chakraborty, Angsuman Sarkar, "Staggered Heterojunctions based Nanowire Tunneling Field Effect Transistors for Analog/Mixed-Signal System-On-Chip Applications", Nano brief reports and reviews, Vol. 10, No. 2, Page: 1550027 1-7, 13 January 2015,© World Scientific Publishing Co., Impact Factor: 1.36

4. Avik Chakraborty, Angsuman Sarkar, "Investigation of Analog/RF performance of Staggered Heterojunctions Based nanowire Tunneling Field-Effect Transistors", Superlattices and Microstructures, Volume 80, Page: 125-135, April 2015 © Elsevier B.V, Impact Factor: 2.097

5. Biswajit Baral, Aloke Kumar Das, Debashis De and Angsuman Sarkar, "An analytical model of triple-material double-gate metal–oxide–semiconductor field-effect transistor to suppress short-channel effects ", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 2015, Willey Online Library, ©John Wiley & Sons, Ltd., USA, Published Online first on 09 January, 2015, Impact Factor: 0.75

6. Siddhartha Mondal, Debabrata Naru, Angsuman Sarkar, and Chandan Kumar Sarkar, "An Analytical Surface Potential Based Threshold Voltage Model of Triple Material Surrounding Gate Schottky Barrier MOSFET", Journal of Computational and Theoretical Nanoscience, American Scientific Publishers, USA, Vol. 12, 1–9,February 1, 2015, Impact Factor: 1.032 

7. Sudhansu Mohan Biswal, Biswajit Baral, Debashis De, Angsuman Sarkar, Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE, Superlattices and Microstructures, Vol. 82, June 2015, Page: 103-112, Impact Factor: 2.097

8. Avik Chakraborty and Angsuman Sarkar,"An Analytical Model for Quantum Confinement in Silicon Nanowires", Quantum matter, American Scientific Publishers, USA, Vol. 5, No. 1, 135-138, 2016

2014 (4)

1. Angsuman Sarkar, Rohit Jana, "The influence of gate underlap on analog and RF performance of III–V heterostructure double gate MOSFET", Superlattices and Microstructures, Vol. 73, September 2014, Page: 256-267 © Elsevier B.V, Impact Factor: 2.097

2. Angsuman Sarkar, "Study of RF performance of surrounding gate MOSFET with gate overlap and underlap", Advances in Natural Sciences: Nanoscience and Nanotechnology, Vol. 5, No. 3, Pages 035006- 1-6, July 2014,© IOP (Institute of Physics) Science, UK

3. Arobinda Pal, Angsuman Sarkar, "Analytical study of Dual Material Surrounding Gate MOSFET to suppress short-channel effects (SCEs)", Engineering Science and Technology, an International Journal, Vol. 17, No. 4, Page: 205-212 © Elsevier B.V, December 2014

4. Swapnadip De, Angsuman Sarkar, "A Study of the Characteristic parameters for Deep Submicron MOSFETs", IUP Journal of Electrical & Electronics Engineering. Vol. 7, No. 1, Page: 41-52, Jan 2014

2013 (2)

1. Angsuman Sarkar, Swapnadip De, Chandan Kumar Sarkar, “Asymmetric halo and symmetric Single-Halo Dual-Material Gate and Double-Halo Dual-Material Gate n-MOSFETs characteristic parameter modeling”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 26, No 1, pp. 41-53, January-February 2013, Willey Online Library, ©John Wiley & Sons, Ltd., USA, Impact Factor: 0.63

2. Angsuman Sarkar, C.K. Sarkar " RF and analogue performance investigation of DG tunnel FET", International Journal of Electronics Letters , Vol. 1, No. 4, Page: 210-217, 2013, Taylor & Francis Group, UK

2012 (9)

1. Angsuman Sarkar, Swapnadip De, Anup Dey, Chandan Kumar Sarkar, “1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model”, IET Circuits, Devices & Systems, The Institution of Engineering & Technology (IET), UK, Vol.6, No.1, pp.28-34, January 2012, Impact Factor: 0.91

2. Angsuman Sarkar, Swapnadip De, Anup Dey, Chandan Kumar Sarkar, “Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model”, Journal of Computational Electronics, Springer Verlag, US, ©Springer Science+Business Media, LLC 2012, Vol. 11, Issue 2, pp. 182-195, June 2012, Impact Factor: 1.520

3. Angsuman Sarkar, Aloke Kumar Das, Swapnadip De, Chandan Kumar Sarkar, “Effect of gate engineering in double-gate MOSFETs for analog/RF applications”, Microelectronics Journal, vol. 43, no. 11, pp. 873-882, November 2012 © Elsevier B.V, Impact Factor: 0.92

4. Angsuman Sarkar, Swapnadip De, Anup Dey, Chandan Kumar Sarkar, “A new analytical subthreshold model of SRG MOSFET with analogue performance investigation”, International Journal of Electronics, Taylor & Francis Group, UK, Vol. 99, No. 2, February 2012, Page: 267-283,Impact Factor: 0.75

5. Swapnadip De, Angsuman Sarkar, “Fringing Capacitance Based Surface Potential Model For Pocket DMG n-MOSFETs”, Journal of Electron Devices (JED),France, Vol. 12, 2012, pp. 704-712, 

6. Swapnadip De,Angsuman Sarkar, Chandan Kumar Sarkar, “Threshold voltage and drift-diffusion theory based drain current model for pocket-DMG n-MOSFETs with inner fringing field”, Journal of Electron Devices (JED), France, Vol. 12, 2012, pp. 767-771

7. Swapnadip De, Angsuman Sarkar, Chandan Kumar Sarkar, “Application of Gaussian profile based DHDMG n-Mosfets on deep submicron microelectronic circuits”, International Journal of Applied Engineering Research,Research India Publication, India, Vol. 7, No.5, Page: 471-483, May 2012, Impact Factor: 0.035

8. Swapnadip De,Angsuman Sarkar, Chandan Kumar Sarkar, “Quasi-Fermi potential based analytical subthreshold drain current and transconductance model for practical DHDMG n-Mosfet”, International Journal of Applied Engineering Research, Research India Publication, India, Vol. 7, No. 7, April 2012

9. Swapnadip De,Angsuman Sarkar, “Modelling of characteristic parameter for submicron mosfet”, IUP Journal of Electrical and Electronics Engineering, IUP Publications India, Vol. 5,No. 3, Page: 67-76, July 2012

2011 (2)

1. Swapnadip De,Angsuman Sarkar, Chandan Kumar Sarkar, “Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs”, International Journal of Electronics, Taylor & Francis Group, UK, Vol. 98, No. 10, October 2011, Page: 1365-1381, Impact Factor: 0.75

2. Swapnadip De,Angsuman Sarkar, Chandan Kumar Sarkar, “Design of a low power low voltage full adder”, International Journal of VLSI Design, International Sciences Press, Serial Publication, India, Vol. 2, No. 2, Page: 103- 106, 2011

2010 (2)

1. Swapnadip De, Angsuman Sarkar, Chandan Kumar Sarkar, “Modeling of thermal and flicker noise for double gate MOSFET”, Journal of Electron Devices (JED), France, Vol. 8, 2010, pp. 320-324

2. Swapnadip De,Angsuman Sarkar, “Thermal and Flicker Noise Modeling of a Double Gate MOSFET”, International Journal on Electronic and Electrical Engineering (IJEEE), Scientific Engineering Research Corporation, India, Summer edition 2010, Vol. 10, No. 01, pp. 24-28

2009 (3)

1. Angsuman Sarkar, Swapnadip De,Chandan Kumar Sarkar, “Subthreshold Surface Potential Model for a Double-Halo Dual-Material GATE And a Single Halo Dual-Material GATE MOSFET”, International Journal on Electronic and Electrical Engineering (IJEEE), Scientific Engineering Research Corporation, India, Spring edition 2009, Vol. 2, No. 2, pp. 25-33

2. Swapnadip De,Angsuman Sarkar,Chandan Kumar Sarkar, “Modeling of subthreshold surface potential in short channel, LAC, Double Halo & DMG MOSFETs with inner fringing fields”, International Journal on Electronic and Electrical Engineering (IJEEE), Scientific Engineering Research Corporation, India, Spring edition 2009, Vol. 01, No. 01, pp. 133-141

3. Swapnadip De,Angsuman Sarkar, Chandan Kumar Sarkar, “Subthreshold surface potential model for a single-Halo dual-material gate  MOSFET”, International Journal on Electronic and Electrical Engineering (IJEEE), ISSN 0974-2042, Scientific Engineering Research Corporation, India, Spring edition 2009, Vol. 01, No. 01, pp. 14-18