Conference Publication

Total :68

2023 (7)

1. M. K. Mahata, S. Chatterjee, T. Das and A. Sarkar, "Device Performance Analysis for Different Gate Locations in AlGaN/GaN HEMT by Silvaco Simulation," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 119-123, doi: 10.1109/DevIC57758.2023.10134979.

2. J. C. Das, D. De, B. Debnath and A. Sarkar, "Single Layer Design of Dual Banyan Network Using Quantum-Dot Cellular Automata," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 182-185, doi: 10.1109/DevIC57758.2023.10134926.

3. A. Kundu, J. C. Das, D. De, B. Debnath and A. Sarkar, "Design of Secure Reversible Select, Cross and Variation (RSCV) Architecture in Quantum Computing," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 243-247, doi: 10.1109/DevIC57758.2023.10134998.

4. A. Basak, A. Deyasi and A. Sarkar, "Analytical Modeling of Asymmetric Junctionless Dual Material Double Gate MOSFET with Underlap for Enhanced Hot Carrier Reliability," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 516-521, doi: 10.1109/DevIC57758.2023.10134835.

5. R. Ghoshhajra, K. Biswas, M. Sultana and A. Sarkar, "Ensemble Learning strategy in modeling of future generation nanoscale devices using Machine Learning," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 546-550, doi: 10.1109/DevIC57758.2023.10134917.

6. S. Bhattacharya, A. Kundu, D. Chakraborty, A. Sarkar, S. Biswas and M. Mukherjee, "Photo-electric Characteristics Analysis of Quantum Corrected Strained Nanowire Drift-Diffusion Model based Si/Si0.98C0.02 Asymmetrical Super-lattice Near Infrared Photo-detector," 2023 4th International Conference on Computing and Communication Systems (I3CS), Shillong, India, 2023, pp. 1-3, doi: 10.1109/I3CS58314.2023.10127313.

7. J. Chowdhury, A. Sarkar, J. K. Das and K. Mahapatra, "Tunnel FET based Standard Logic Cell Implementation: A Circuit Perspective," 2023 2nd Edition of IEEE Delhi Section Flagship Conference (DELCON), Rajpura, India, 2023, pp. 1-5, doi: 10.1109/DELCON57910.2023.10127359.

2022 (6)

1. A Sarkar, A Das, A Das, "Comparative Analysis of Two-Stage Miller Compensated OPAMP in Bulk CMOS and FinFET Technology", Micro and Nanoelectronics Devices, Circuits and Systems, 13-23

2. A. Basak and A. Sarkar, "Analytical Modeling of Asymmetric Gate Stack Junctionless Dual Material Surrounding Gate MOSFET for Enhanced Hot Carrier Reliability," 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 2022, pp. 241-246, doi: 10.1109/EDKCON56221.2022.10032874.

3. T. Das, A. Sarkar and M. K. Mahata, "Performance Analysis of New Dual-Pocket Tunnel-FET-based Biosensor," 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 2022, pp. 405-408, doi: 10.1109/EDKCON56221.2022.10032953.

4. S. Datta, A. Deyasi and A. Sarkar, "Analytical Investigation of Gate-to-Drain Leakage Current for Junctionless Accumulation-Mode MOSFET," 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 2022, pp. 607-610, doi: 10.1109/EDKCON56221.2022.10032862.

5. I. Banerjee, S. Bhattacharyya and A. Sarkar, "Analytical Modeling of Dielectric Modulated Triple Material Stacked Surrounding Gate Junctionless MOSFET based label free Biosensor," 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 2022, pp. 626-631, doi: 10.1109/EDKCON56221.2022.10032806.

6. S. Dey, K. Biswas and A. Sarkar, "State of the Art and Future Perspectives in III-V Nanometer-Scale MOSFETs," 2022 IEEE VLSI Device Circuit and System (VLSI DCS), Kolkata, India, 2022, pp. 170-175, doi: 10.1109/VLSIDCS53788.2022.9811490.

2021 (6)

1. R. Dhar, A. Deyasi and A. Sarkar, "Generation of Tunable Low-noise Millimeter-wave Signal using Optical Frequency Comb through Electrical Mixing at 94 GHz," 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 13-18, doi: 10.1109/DevIC50843.2021.9455808. 

2. R. Das, A. Deyasi and A. Sarkar, "Computing Electromagnetic Bandgap for Parallel Nanorod Structure with Double Negative Refractive Index inside Triangular Lattice," 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 50-52, doi: 10.1109/DevIC50843.2021.9455920.

3. P. Mitra, J. Bhaumik and A. Sarkar, "Power Supply Noise Aware Physical Design with Decoupling Capacitance Allocation in System-on-Chip," 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 166-169, doi: 10.1109/DevIC50843.2021.9455918.

4. R. Ghoshhajra, K. Biswas and A. Sarkar, "A Review on Machine Learning Approaches for Predicting the Effect of Device Parameters on Performance of Nanoscale MOSFETs," 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 489-493, doi: 10.1109/DevIC50843.2021.9455840.

5. A. Mukherjee, D. Banerjee, T. Ganguli and A. Sarkar, "Analysis of Double-Gate Junctionless MOSFET for Energy Efficient Digital Application," 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 545-549, doi: 10.1109/DevIC50843.2021.9455793.

6. N. Chand, S. K. Swain, S. M. Biswal, A. Sarkar and S. Adak, "Comparative study on Analog & RF Parameter of InAlN/AlN/GaN Normally off HEMTs with and without AlGaN Back Barrier," 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 616-620, doi: 10.1109/DevIC50843.2021.9455877.

2020 (9)

1. A Deyasi, S Mukhopadhyay and A Sarkar, Novel Analytical Model for Computing Subthreshold Current in Heterostructure p-MOSFET incorporating Band-To-Band Tunneling Effect, Published under licence by IOP Publishing Ltd, Journal of Physics: Conference Series, Volume 1579, National Conference on Frontiers in Modern Physics 6-7 February 2020, Adamas University, Kolkata, India

2. J Chowdhury, AD Deyasi, A Sarkar, K Mahapatra, Novel Threshold Voltage Model Incorporating Band-to-Band Tunneling in Heterostructure p-MOSFET, 2019 IEEE International Symposium on Smart Electronic Systems (iSES)(Formerly iNiS)m, Pages 373-376, IEEE xplore

3. N. Pramanik, A. Deyasi and A. Sarkar, "Design of Photonic Filter Using Metamaterial Based Defected Ternary Structure Under Normal Incidence," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 46-49.

4. P. Debnath, A. Deyasi, U. Mondai and A. Sarkar, "Improved Loss Characteristic in 1-bit RF MEMS Switch owing to Lower Dielectric Constant," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 56-59.

5. A. Basak and A. Sarkar, "Analytical Modeling of Asymmetric Junctionless DMDG MOSFET for Suppressing Short Channel Effects," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 79-83.

6. K. Biswas, A. Sarkar and A. Sarkar, "Effect of Channel Doping and Fin Shapes on Performance of Junctionless Bulk FinFET," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 267-270.

7. P. Mitra, P. Alok and A. Sarkar, "A CAD Approach for Accurate Decap Estimation and Allocation for Supply Noise Reduction in SoC," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 279-282.

8. R. Halder and A. Sarkar, "Performance Evaluation of Double Gate Pentacene Organic FET Using Simulation Study," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 1-4.

9. J. Chowdhury, A. Sarkar, K. Mahapatra and J. K. Das, "Analytical Drain Current Model for Super-Threshold Region of Double Gate Tunnel FET," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 1-4.

2019 (15)

1. A. Basak and A. Sarkar, "Analytical Drain Current Model of UTBB SOI MOSFET with lateral dual gates to Suppress Short Channel Effect," 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 269-274. doi: 10.1109/DEVIC.2019.8783327, Available in IEEE Xplore

2. A. Chakraborty, S. Bhowmick, D. Chakraborty, A. Deyasi and A. Sarkar, "Boundstates Computation for Double Quantum Well Structure with Pöschl-Teller Potential for MWIR Photodetector Design," 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 264-268. doi: 10.1109/DEVIC.2019.8783699, Available in IEEE Xplore

3. S. Adak, N. Chand, S. K. Swain and A. Sarkar, "Effect of AlGaN Back Barrier on InAlN/AlN/GaN E-Mode HEMTs," 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 156-160. doi: 10.1109/DEVIC.2019.8783383, Available in IEEE Xplore

4. P. Debnath, A. Deyasi and A. Sarkar, "Up-state and Down-state Capacitance Measurement in RF MEMS One-bit Switch Designed at Microwave Frequency Range," 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 137-140. doi: 10.1109/DEVIC.2019.8783948, Available in IEEE Xplore

5. P. Chakraborty, R. Ghosh, A. Adhikary, A. Deyasi and A. Sarkar, "Electromagnetic Bandgap Formation in Two-Dimensional Photonic Crystal Structure with DNG Materials under TE Mode," 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 26-29. doi: 10.1109/DEVIC.2019.8783914, Available in IEEE Xplore

6. A. Deyasi, B. Sen, G. Saha and A. Sarkar, "Analytical Investigation of Differential Conductance in Submicron HEMT with Two Different Substrates," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 37-41.doi: 10.1109/EDKCON.2018.8770496, Available in IEEE Xplore

7. Swati Sinha ; Kunal Biswas ; Angsuman Sarkar ; Siddharth Shaw ; Jaya Bandyopadhyay ;Sanjukta Mitra ; Debashis De, "Tuning of Bandstructure of Single—Walled Carbon Nanotube Functionalized with ssDNA Oligonucleotide Sequence," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 651-656. doi: 10.1109/EDKCON.2018.8770444, Available in IEEE Xplore

8. A. Deyasi, A. R. Chowdhury, K. Roy and A. Sarkar, "Effect of High-K Dielectric on Drain Current of ID-DG MOSFET Using Ortiz-Conde Model," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 176-181. doi: 10.1109/EDKCON.2018.8770399, Available in IEEE Xplore

9. S. Paul, S. Mondal and A. Sarkar, "A Novel GaN-Hemt based Inverter and Cascode Amplifier," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 465-469. doi: 10.1109/EDKCON.2018.8770510,,Available in IEEE Xplore

10. M. Mukherjee, M. Chanda, A. Dey and A. Sarkar, "Effect of Band Non-Parabolicity on Energy Sub-Band Profile for Nano-Dimensional MOSFET," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 662-665.doi: 10.1109/EDKCON.2018.8770402, Available in IEEE Xplore

11. A. Basak and A. Sarkar, "Analytical Study of Unipolar Junction Transistor as a Novel Dual Material Double Gate MOSFET to Suppress Short-Channel Effect," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 475-480. doi: 10.1109/EDKCON.2018.8770518, Available In IEEE Xplore

12. A. Banerjee, A. Deyasi, S. Bhattacharyya, and A. Sarkar, "Fast Squaring Technique for Radix Vicinity Numbers for Radix 2n±m with reduced Computational Complexity", SPRINGER: Lecture Notes in Electrical Engineering: Nanoelectronics, Circuits and Communication Systems, vol. 511, chapter 13, pp. 139-147, 2019 [DOI: 10.1007/978-981-13-0776-8_13]

13. K. Roy, A. Roy Chowdhury, A. Deyasi and A. Sarkar, "Computing Surface Potential and Drain Current in Nanometric Double-Gate MOSFET using Ortiz-Conde Model", SPRINGER: Advances in Intelligent Systems and Computing (AISC) Series: Contemporary Advances in Innovative and Applicable Information Technology, vol. 812, chapter 5, pp. 41-47, 2019 [DOI: 10.1007/978-981-13-1540-4_5]

14. A. Deyasi and A. Sarkar, "Blueshift of Optical Signal in PhC based Butterworth Filter due to Joule Heat Dissipation", SPRINGER: CCIS Series: 2nd International Conference on Computational Intelligence, vol. 1030, chapter 28, pp. 352-360, 2019 [DOI: 10.1007/978-981-13-8578-0_28]

15. A. Deyasi, A.Sarkar " Computing optical bandwidth of bandpass filter using metamaterial-based defected 1D PhC", 2019, AIP Conference Proceedings, 2072:1, 10.1063/1.5090243, https://aip.scitation.org/doi/abs/10.1063/1.5090243

2018 (1)

1. A. Deyasi, P. Verma, and A. Sarkar, "Calculating Transmittance and Field Enhancement of nLayer MIM Surface Plasmon Structure for Detection of Biological Nano-objects", SPRINGER: CCIS Series, vol. CCIS 836, chapter 33, pp. 393-401, 2018 [DOI: 10.1007/978-981-13-1343-1_2]

2016 (6)

1. Angsuman Sarkar "Tunnel FET: A Perspective Review for Energy Efficient Applications ", Technical Magazine of IEEE EDS Kolkata Chapter, Volume 1, No. 1, pp. 6-10, January 2016

2. Swati Sinha, Kunal Biswas, Debashis De, Jaya Bandopadhay, Angsuman Sarkar, "Metal to Semimetal conversion by bandgap engineering of SWCNT by DNA nucleobase functionalization", Proceeding of MICRO-2016, TEQIP-II, WBUT sponsored 3rd Int. Conference on Microelectronics, Circuits and Systems on 09-10th July , 2016 at Science City, Kolkata, ISBN : 978-93-80183-45-5

3. Surajit Bari, Debashis De and Angsuman Sarkar, "Average power consumption and delay analysis of 4 bit binary to grey code converter circuit using nano dimensional MOS transistors" Proceeding of MICRO-2016, TEQIP-II, WBUT sponsored 3rd Int. Conference on Microelectronics, Circuits and Systems on 09-10th July , 2016 at Science City, Kolkata, ISBN : 978-93-80183-45-5

4. A Chakraborty, A Sarkar, "Analytical modeling and sensitivity analysis of dielectric-modulated junctionless gate all around gate stack—FET as biosensor", Book Computational Science and Engineering: proceedingss of the International Conference on Computational Science and Engineering (ICCSE2016), Beliaghata, Kolkata, India, 4-6 October 2016, Pages 273-276, Publisher: CRC Press

5. M. Chanda, P. Dey, A. Sarkar and C. K. Sarkar, "Doping-less double gate impact ionization MOSFET for high switching application," 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, India, 2016, pp. 179-183.doi: 10.1109/ICDCSyst.2016.7570589, available in IEEE Xplore

6. K. Biswas, A. Sarkar and C. K. Sarkar, "Performance assessment of Indium Arsenide (InAs) Single and Dual quantum-well heterostructure FinFETs," 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, India, 2016, pp. 208-211.doi: 10.1109/ICDCSyst.2016.7570650, available in IEEE Xplore

2015 (5)

1. Sayantan Mondal and Angsuman Sarkar, Analytical subthreshold modeling of dual material gate engineered junctionless surrounding gate MOSFET considering ECPE, 1st International Conference On Emerging Trends in Computer Science and Information Technology ETCSIT-2015, Kalyani Government Engineering College, India 06-January-2015

2. Tauseef Ahmed and Angsuman Sarkar, Scaling theory of Dual Material Junctionless Double Gate nanoscale MOSFET considering Effective Conduction Path Effect, , 1st International Conference On Emerging Trends in Computer Science and Information Technology ETCSIT-2015, Kalyani Government Engineering College, India 06-January-2015

3. Angsuman sarkar, Effect of  gate-length downscaling on RF/analog performance of a junctionless double gate MOSFET for analog/mixed signal system-on-chip applications" at FASSMATA-2015 organized by Dept. of ECE and Dept. of BS & HU held during 6th to 10th july, 2015 at RCC Institute of technology, Kolkata.

4. Surajit Bari, Sonali Bhowmik, Debashis De and Angsuman Sarkar "Design and Power Analysis of 4×4 Semiconductor ROM array at 32nm,22nm, and 16nm channel length of MOS transistor" Published in the proceedings of 2nd International Conference on Microelectronics ,Circuits and Systems , MICRO-2015 , Organized by International Association of Science ,Technology and Management , 11th July - 12th July ,2015, ISBN :81-85824-46-0, pp 32-35, Vol-I.

5. Surajit Bari, Arko Bhowmick, Debashis De and Angsuman Sarkar "Design and Power Consumption Analysis of  Hardware Pattern Generator using LFSR for BIST using Nano Scale  MOS transistor"  Published in the proceedings of 2nd International Conference on Microelectronics ,Circuits and Systems , MICRO-2015 , Organized by International Association of Science ,Technology and Management , 11th July - 12th July ,2015, ISBN :81-85824-46-0, pp 41-45,Vol-II. 

2014 (4)

1. Rohit Jana, Angsuman Sarkar, THE IMPACT OF GATE UNDERLAP ON ANALOG & RF PERFORMANCE OF HETERO-JUNCTION FET, International Conference on Intelligent Computing, Communication & Devices (ICCD 2014), SOA University, Bhubaneswar, Odisha, India, 18th April 2014

2. Soumen Paul, Angsuman Sarkar, An analytical surface potential model of Surrounding Gate Tunnel FET, International Conference on Intelligent Computing, Communication & Devices (ICCD 2014), SOA University, Bhubaneswar, Odisha, India, 18th April 2014

3. Biswajit Baral, Sudhansu Mohan Biswal, Debashis De and Angsuman Sarkar, Effect of gate length downscaling on RF/Analog and Linearity performance of a Junctionless Double Gate MOSFET for Analog/mixed signal System-on-chip applications, 3rd International Conference on Nanotechnology Nanocon 2014, Pune, India, 14th October, 2014

4. Sudhansu Mohan Biswal, Biswajit Baral, Debashis De and Angsuman Sarkar, Study of effect of gate-length downscaling on the Analog/RF performance of Tunnel FET, 3rd International Conference on Nanotechnology Nanocon 2014, Pune, India 14th October, 2014

2013 (1)

1. Swapnadip De, Angsuman Sarkar, Manash Chanda, Chandan Kumar Sarkar, " Study of Surface Potential and Threshold Voltage for non-uniformly doped DHDMG n-MOSFET", 4TH INTERNATIONAL CONFERENCE ON TECHNICAL AND MANAGERIAL INNOVATION IN COMPUTING AND COMMUNICATIONS IN INDUSTRY AND ACADEMIA(IEMCON 2013), Kolkata; 08/2013

2012 (4)

1. Swapnadip De, Manash Chanda, Angsuman Sarkar , Analytical Sub-threshold Surface Potential and Drain Current Model for Linearly Doped Double Halo DMG MOSFET NCACD 2012,SPONSORED BY DRDO,CSIR, HALDIA iNSTITUTE OF TECHNOLOGY; 09/2012

2. Priyanka Chakraborty, Angsuman Sarkar, “Investigation and comparison of noise suppression in speech signals using LMS and RLS algorithms”, RACCCT2012, National Conference on Recent Advances in control , communication and computing technologies, organized by IEEE SCET SB, SCET, Surat, India, March 29-30, 2012, Proceedings of RACCCT2012, pp. – 266-269

3. Rohan Dutta, Angsuman Sarkar, “A Comparative Performance Study of Adaptive Filtering in Noise Cancellation using Anti-Noise between Conventional and two new LMS Algorithms”, RACCCT2012, National Conference on Recent Advances in control , communication and computing technologies, organized by IEEE SCET SB, SCET, Surat, India, March 29-30, 2012, Proceedings of RACCCT2012,pp. – 270-273

4. Joydeep Kushari,Angsuman Sarkar, “Variable Step-Size NLMS and Affine Projection Algorithms for Echo Cancellation: A Comparative Study”, RACCCT2012, National Conference on Recent Advances in control , communication and computing technologies organized by IEEE SCET SB, SCET, Surat, India March 29-30, 2012, Proceedings of RACCCT2012,pp. – 274-279

2011 (1)

1. Aloke Kumar Das, Angsuman Sarkar, “A systemic investigation of short channel effects for triple material double gate(TM-DG) MOSFET”, IEEE EDS STUDENT PAPER CONFERENCE (IESPC) 2011, Heritage Institute of Technology, Kolkata, India, April 18, 2011

2009 (1)

1. Angsuman Sarkar, Swapnadip De, Mohankumar Nagarajan, C. K. Sarkar, “Surface potential model in short channel MOSFET including effect of fringing field operating in subthreshold region”, NATIONAL CONFERENCE ON Recent Development in Applied Mathematical Science and Engineering, Jalpaiguri Government Engineering College, West Bengal, India, 20 – 22 Feb 2009

2008 (2)

1. Angsuman Sarkar, Swapnadip De, Mohankumar Nagarajan, C. K. Sarkar, Srimanta Baishya, “Effect of fringing fields on subthreshold surface potential of channel engineered short channel MOSFETS”, TENCON 2008, IEEE Region 10 Conference, Hyderabad, India, pp.1-6, 19-21 Nov. 2008

2. Swapnadip De, Angsuman Sarkar, Mohankumar Nagarajan, C. K. Sarkar, “Effect of fringing field in modeling of subthreshold surface potential in dual material gate (DMG) MOSFETS”, ICECE 2008, IEEE, International Conference, Electrical and Computer Engineering, 2008, Dhaka, Bangladesh, On page(s): 148 – 151, 20-22 Dec. 2008