Research Area

As device scaling continues to sub-100nm regime, it is become crucial to identify the detrimental short-channel effects and their remedies. Therefore, the study of short-channel effects and their remedies is a principal problem of great magnitude in the perspective of integrated circuit (IC) manufacturing and related reliability issues.The research interest of Dr. Sarkar spans around the study, discussion and investigation of the effect of diminishing MOS channel length on device characterizes and their remedies by novel unconventional device structures, highlighting his concept of MOSFET device physics and knowledge of scaling trends in MOSFET evolution using device modeling and TCAD simulation.It is also equally important to identify the analog/RF characteristics of the novel device structures, envisioned as a future replacement of silicon planar MOSFETs in digital circuits and is a potential candidate for providing long-term solutions to continue scaling CMOS beyond the 100-nm technology node, in order to use them in in a mixed-signal System-on-Chip (SoC) applications.

Research Interests:

  1. Nano Electronics

  2. MOS Device Physics

  3. Scaling of MOSFET

  4. Nano-scale MOSFET Modelling & Simulation

  5. TCAD device Simulation (Silvaco)

  6. RF/Analog Performance investigation of novel MOS device structures

  7. CMOS Technology