Running CAD Simulations
Created by
Madhava Vemuri
Madhava Vemuri
Create a new project using the Data-Flow modeling of and gate
Here is the VHDL code for the AND gate using the data-flow modeling. Copy the following code into a new project
-- The following is a data flow implementation of 2 input AND gate with
-- A, B: single logic input
-- C: single logic output
-- library definitions here
library ieee;
use ieee.std_logic_1164.all;
-- Entity declarations are specified here
entity and_gate is
port(
A, B: in std_logic;
C : out std_logic);
end and_gate;
-- Architecture of the specified entity is created here
architecture and2_arch of and_gate is
begin
C <= A and B;
end and2_arch;
Simulate the specification using the Modelsim software. To open the simulation tool select: Tools > Run Simulation Tool > RTL simulation. If you see the following window the paths to the simulation software has not been set.
To modify the path select: Tools > Options > EDA Tool Options. The following dialog box opens.
Select the path to the Modelsim-Altera software. Click Ok
<path to quartus installation>\modelsim_ase\win32aloem
Open the simulation tool again using : Tools > Run Simulation Tool > RTL simulation. If the path you have specified is correct, the Modelsim-altera application will open
Under the work section in the library you should see the entity of the top most hierarchy you have created.
Right Click in the entity select simulate, you should see input and output ports listed under objects.
Create the waves on the input ports using by right clicking on a input port. Right Click > Modify > Apply Wave. You should see the following dialog box
Start Time and End Time specifies the simulation time for the wave you are created. In the above the wave terminates after 1000 ps. Specify the simulation time and Click Next >
Clock pattern is created for this instance with a Clock Period of 100 ps. The Duty cycle here is a percentage of on time.
Clock Period: 100ps
Duty Cycle: 50%
T_on: 50ps
T_off: 50ps
Initial value: Undefined (U)
Create another wave with 2x the period for another input port. You should see the following wave patterns in the wave window
Add the output port onto the wave window to look at the outcome of the gate simulation
Change the run length to simulate for longer run times (1000 ps) and Click run (blue highlight)
You should see the following simulated outcome in the wave window
Exit the application, you can choose to save waves you have created while exiting. You can use these waves to save the