INSTRUCTION FORMAT FOR IMMEDIATE ADDRESSING MODE

Learning Outcome:

Understand instruction formats for different addressing modes and implement an instruction lifecycle.

Tasks:

1. Define instruction formats for immediate, direct, register, and indirect addressing.

2. Simulate instruction fetch-decode-execute-write back cycle.

Immediate Addressing Mode

Immediate Addressing Mode is one of the simplest and most commonly used addressing modes in a computer's instruction set architecture (ISA). In this mode, the operand (the data to be processed) is directly specified within the instruction itself, rather than being stored in a register or memory location. This allows for fast access to the operand, as it is provided as part of the instruction.

Key Features of Immediate Addressing Mode:

Operand in Instruction:
- In immediate addressing mode, the operand is included directly within the instruction. The operand is typically a constant value (immediate value) used in arithmetic, logical, or other operations.
- For example, an instruction might look like ADD R1, #5, where #5 is the immediate operand (the number 5) and R1 is the register that will be updated with the result.
No Memory Access:
- Since the operand is part of the instruction, there is no need to access memory locations or registers to fetch the operand. This results in faster execution because the operand is immediately available to the processor.
Simplicity:
- This addressing mode is simple to implement because the operand is already embedded within the instruction, eliminating the need for additional memory access or register operations to fetch the operand.
Limited Operand Size:
- The operand in immediate addressing mode is typically limited to a small size due to the constraints of the instruction format. For example, it might only be a fixed number of bits, such as 8, 16, or 32 bits, depending on the architecture.
Usage in Operations:
- Immediate addressing mode is often used for operations like initialization, where a constant value needs to be directly loaded into a register or used in a computation. For example, adding a constant value to a register, setting a value in a register, or comparing a register to a constant.

CENTRAL PROCESSING UNIT :-

1. Key Components of the CPU

Program Counter (PC): Holds the address of the next instruction to execute.
Memory Address Register (MAR): Sends the address to fetch the instruction or data from memory.
Memory Buffer Register (MBR): Temporarily stores fetched instructions or data from memory.
Instruction Register (IR): Holds the current instruction being decoded and executed.
Control Unit (CU): Decodes instructions and generates control signals to coordinate operations.
Register File: Contains general-purpose registers (RA, RB, RZ) for storing operands and results.
ALU (Arithmetic Logic Unit): Performs arithmetic and logic operations.
Code Memory (ROM): Stores program instructions.
Clock: Synchronizes the operation of all components.

2. 2-Address Format

In the 2-address instruction format, each instruction has:

One destination address (where the result is stored).
One source address (where one of the operands is stored).

For example:

Instruction: ADD RA, RB
- RA = RA + RB (result is stored in RA).

Steps:

The PC provides the address of the instruction in memory.
The instruction is fetched and stored in the IR.
The CU decodes the instruction to identify:
- The operation (ADD).
- The operands (RA and RB).
The CU sends control signals to read RA and RB from the register file.
The ALU performs the operation (e.g., addition).
The result is written back to RA.

3. Immediate Addressing Mode

In immediate addressing mode, the operand is directly embedded in the instruction itself.

For example:

Instruction: ADD RA, #5
- RA = RA + 5 (5 is the immediate value).

Steps:

The instruction is fetched into the IR.
The CU decodes the instruction and extracts:
- The operation (ADD).
- The operand register (RA).
- The immediate value (#5).
The CU sends control signals to fetch RA from the register file.
The immediate value (5) is sent directly to the ALU.
The ALU adds the value to RA and stores the result back in RA.

4. 2-Stage Pipeline

The CPU implements a simple 2-stage pipeline to improve performance:

Fetch Stage:
- The instruction is fetched from memory (address from the PC) and stored in the IR.
- At the same time, the PC is incremented to point to the next instruction.
Execute Stage:
- The CU decodes the instruction.
- Operands are fetched from the register file or extracted (immediate values).
- The ALU performs the required operation.
- The result is written back to the destination register.

This pipelining allows the CPU to fetch the next instruction while executing the current one, thus overlapping operations and increasing throughput.

Working Example in the Diagram

The PC sends the address of the instruction to the MAR.
The Code Memory fetches the instruction and stores it in the MBR, then loads it into the IR.
The CU decodes the instruction:
- If it is a 2-address instruction (e.g., ADD RA, RB):
  - Both RA and RB are read from the register file.
  - The ALU performs the operation, and the result is written back to RA.
- If it is an immediate instruction (e.g., ADD RA, #5):
  - RA is read from the register file.
  - The immediate value (5) is added using the ALU, and the result is written back to RA.
The pipeline ensures the fetch of the next instruction occurs while the current one executes.