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INSTUCTION STATE DIAGRAM
INSTUCTION STATE DIAGRAM
The Instruction Cycle State Diagram, including interrupts, illustrates the sequence of operations a CPU performs to execute instructions. Here’s a concise breakdown of each stage:
Instruction Fetch: The CPU retrieves the next instruction from memory.
Instruction Address Calculation: Calculates the address of the next instruction to fetch.
Instruction Operation Decoding: Decodes the instruction to determine the operation and required operands.
Operand Address Calculation: Computes the memory addresses of the operands needed for the operation.
Operand Fetch: Fetches operands from memory or registers; may involve additional address calculations for indirect addressing.
Data Operation: Executes the specified operation, such as arithmetic, logical, or data manipulation.
Operand Store: Writes the result back to memory or a register, with further address calculations if needed.
Instruction Complete: After completing the current instruction, the CPU fetches the next instruction, restarting the cycle.
INSTRUCTION 1
INSTRUCTION 1
SUB R0,#0X002
SUB R0,#0X002
ADD R0,#0X02
STOR R5,#0X000
INSTRUCTION 2 :-
INSTRUCTION 2 :-
DIV R1,#0X002
SUB R1,#OX003
STOR R5,#0X00
INSTRUCTION 3 :-
INSTRUCTION 3 :-
AND R1,#0X02
SHR R1,#0X02
STOR R8,#0X00
INSTRUCTION 4:-
INSTRUCTION 4:-
OR R1,#0X002
SHL R1,#0X003
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